What are the responsibilities and job description for the Staff Engineer - FPGA RTL Developer position at A3?
Description
We are seeking an experienced Senior RTL Engineer to join our hardware design team. This role requires a strong foundation in Verilog / SystemVerilog and C / C programming, with extensive experience in FPGA design, simulation, and optimization. The ideal candidate will be skilled in static timing analysis, FPGA constraints, and embedded system development within a Linux-based design environment. As a Senior RTL Engineer, you will work closely with cross-functional teams to develop, test, and optimize FPGA and SoC-based solutions for high-performance applications.
Major Duties & Responsibilities
- Develop RTL designs using Verilog and SystemVerilog for complex digital systems.
- Write and integrate embedded software in C or C for hardware interaction, testing, and debugging.
- Collaborate with software and firmware teams to ensure seamless integration of hardware and software components.
- Constrain FPGAs for static timing analysis and optimize FPGA builds for performance, resource usage, and power efficiency.
- Conduct RTL simulations to verify functionality, reliability, and timing.
- Collaborate with cross-functional teams, including hardware, software, and QA, to ensure project success.
Minimum Skills & Abilities
Minimum Education & Experience
