What are the responsibilities and job description for the Design Verification Engineer position at Abhyanth Solutions?
Job Details
Job Title: Design Verification (DV) Engineer
Location: Bay Area, CA
Job Type: Long Term Contract
Experience: 10 years
Job Description:
We are seeking a highly skilled Design Verification (DV) Engineer to join our team in the Bay Area, CA, for a long-term contract opportunity. The ideal candidate will have over 10 years of experience in the field, with a strong background in Networking and SERDES verification. This role requires expertise in verification techniques, beyond just SystemVerilog (SV) and UVM.
Key Responsibilities:
- Develop and execute comprehensive verification plans for complex designs, focusing on Networking and SERDES protocols.
- Create testbenches, write functional and performance verification code, and contribute to the overall verification strategy.
- Collaborate with cross-functional teams to ensure design correctness and performance optimization.
- Perform rigorous functional verification using advanced methodologies and tools.
- Utilize knowledge of SERDES protocols and networking concepts for effective design verification.
- Identify and troubleshoot design issues, documenting defects and working with the design team to resolve them.
Required Skills and Experience:
- 10 years of experience in Design Verification (DV) roles, with a solid track record of successful project delivery.
- In-depth knowledge and hands-on experience in Networking and SERDES verification.
- Strong understanding of verification methodologies beyond SV/UVM.
- Proficiency in verification languages such as SystemVerilog (SV) and experience in UVM.
- Excellent analytical, debugging, and problem-solving skills.
- Ability to work independently and collaborate effectively with teams.
If you meet the qualifications above and are ready for a challenging yet rewarding contract opportunity, we encourage you to apply. Please share your expected rate for consideration.
