What are the responsibilities and job description for the Design for Test Engineer position at Acceler8 Talent?
Design for Test Engineer
We are seeking an experienced Design-for-Test (DFT) Engineer to join our high-performing team in San Francisco, helping us create best-in-class silicon for high-performance and sustainable Generative AI.
Founded by engineers who have been instrumental in the industry's most successful semiconductor and AI products, our company is pushing the boundaries of what Large Language Models can accomplish. With a team comprised of industry veterans, talent and passion are the foundational pillars behind our success.
As a Silicon DFT Engineer, you would execute our DFT implementation/verification and collaborate on physical design methodology from RTL to GDS. You would integrate DFT interfaces from IP blocks, develop pattern porting flow, and identify and execute efficient and effective DFT solutions based on chip architecture.
This role may be ideal for you if you have:
- Experience with DFT implementation (MBIST and At-speed Scan) and executing on large and complex ASICs and SOCs to produce silicon
- Worked with the latest DFT technologies (IJTAG, Streaming Scan, etc.)
- Automated DFT flow / worked with Tessent DFT & Fusion Complier
- Familiarity with the integration of PHY DFT interfaces
This is a hybrid role based in the San Francisco Bay Area.
