What are the responsibilities and job description for the Design Verification Engineer position at Acceler8 Talent?
Design Verification / Principal Emulation Engineer
Acceler8 Talent is seeking an experienced Design Verification / Principal Emulation Engineer to join a high-performing San Francisco-based team, helping them create best-in-class silicon for high-performance and sustainable Generative AI. If you’re looking to make an impact in this exciting age of technological advancement, this opportunity may be for you!
Founded by engineers who have been instrumental in the industry’s most successful semiconductor and AI products, this company is pushing the boundaries for what LLMs can accomplish. With a team comprised of industry veterans, talent and passion are the foundational pillars behind their success.
As the Principal Emulation Engineer, you'll lead the effort to build comprehensive hardware emulation frameworks and execute emulation test plans. You’ll be contributing to the verification methodology and execution across blocks, subsystems, full chip, and system-level validation. You’ll own portions of the verification execution at the subsystem and chip level, creating test benches and executing progress and verification closures toward various silicon milestones.
This role might be ideal for you if you have :
- Developed, debugged, and deployed emulation-based prototyping platforms
- Experience driving verification from concept-to-silicon
- Knowledge of LPDDR / HBM
- Production experience with advanced verification methodologies (UVM, AVB, formal verification, etc.)
- Strong understanding of silicon micro-architecture and design concepts used in high-performance compute, high-speed connectivity, memory management, and related functionalities
- 5 years working in design verification roles
This is a hybrid role based in the San Francisco Bay Area.
Base Salary : $200,000 - $300,000 equity benefits
Salary : $200,000 - $300,000
