What are the responsibilities and job description for the Senior DV Engineer position at Acceler8 Talent?
We’re urgently seeking a skilled a DV Engineer to join a Cupertino based start-up. In this role, you will develop and implement testbenches using advanced verification methodologies like UVM, ensuring the functionality and performance of microchip designs. You will work closely with design and architecture teams, utilizing tools like Synopsys VCS and Verdi for functional verification, static timing analysis, and formal verification of microchips. This position requires strong expertise in System Verilog, ASIC development, and debugging, along with the ability to automate verification tasks using Python.
Responsibilities :
- Develop ASIC testbenches using UVM to verify the correct functionality of microchip designs.
- Implement micro-architecture and RTL specifications in System Verilog, maintaining a verification environment for specialized AI microchips.
- Perform functional and performance verification using tools like Synopsys VCS and Verdi, ensuring design meets all requirements.
- Apply static and dynamic methods for design timing closure and run static timing analysis.
- Automate verification tasks using Python for testbench generation, test case creation, and results analysis.
Qualifications :
