Analog Mixed Signal Design Engineer

WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

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THE ROLE:

AMD’s Low Power Advanced Development team is seeking talented, self-motivated individuals to help develop power management circuit design innovations that enable industry-leading power efficient computing and graphics products. We have openings for R&D engineers to serve as key contributors in small project teams working on low power advanced development projects. 

THE PERSON:

A candidate who is seeking challenging projects in power management circuit design using the latest modern semiconductor technologies, who is eager to learn and is a good team player.

KEY RESPONSIBILITIES:

• Working on Adaptive Clock Generators for CPU and/or GPU applications, custom mixed-signal circuits and logic design in advanced CMOS technologies using custom and semi-custom design flows
• Design and Simulate Power Management Circuit Architectures on System level, RTL level and on Transistor level using Matlab, SystemVerilog, Verilog, Verilog-A and Hspice
• Design, simulate, and verify analog, high speed digital, and mixed-signal circuits
• Design for optimum power/speed/area efficiency
• Closely work with and supervise layout/mask designers by providing annotated schematics, floor plans, layout, reliability and manufacturability design guidelines
• Experience in back-end design verification tools and flows including debugging LVS and DRC issues in collaboration with the layout team
• Work in collaboration with Physical Design Engineers in chip level planning and integrations
• Create or in collaboration with other team members design reviews, technical reports, and other documentation required for meeting the design quality and for the tapeout signoff

PREFERRED EXPERIENCE:

• Requires strong understanding of analog/mixed signal/digital design concepts and CMOS processes
• Experience in Phase-Locked Loop (PLL) design, Frequency-Locked Loop (FLL) design, Oscillators, High Speed Clock circuits, Linear and Switching voltage regulators, DAC, voltage comparators
• Knowledge in RTL digital design flows including Verilog HDL is a big plus.
• Knowledge in ADC design is a plus
• Cadence's custom IC design environment with special emphasis on Virtuoso schematic/layout design entry tools
• Analog/mixed signal circuit simulators, specifically Hspice, Spectre, SpectreRF
• Scripting experience is required (python, perl, csh)
• Verilog-A modelling
• Matlab
• Synopsys Custom Designer schematic/layout design entry tool experience is a plus
• Strong communication skills, teamwork experience and a quick learner in a fast-moving environment

ACADEMIC CREDENTIALS:

• MS/PhD Electrical Engineering plus relevant experience 
• Computer Architecture work experience is a plus

LOCATION:

• Austin, Texas

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At AMD, your base pay is one part of your total rewards package.  Your base pay will depend on where your skills, qualifications, experience, and location fit into the hiring range for the position. You may be eligible for incentives based upon your role such as either an annual bonus or sales incentive. Many AMD employees have the opportunity to own shares of AMD stock, as well as a discount when purchasing AMD stock if voluntarily participating in AMD’s Employee Stock Purchase Plan. You’ll also be eligible for competitive benefits described in more detail here.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.