SoC DFT Architect

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THE ROLE: 

As a Design-for-Testability (DFT) design and architect engineer, you should have prior experience in defining the DFT Architecture, methodology flow and DFT implementation verification plan. You also should have DFT end to end execution experience from DFT spec definition to post silicon bringup. You will meet regularly with other functional team members such as Architects, Verification Engineers, Physical Designers, CAD Engineers, SoC Design Engineers, Product Engineers and Program Management to ensure successful and timely project completion.

THE PERSON:

As a member of the Strategic Silicon Solutions (S3) Business Unit within AMD, your execution will help bring to life customers Special requirements for designs to be used in a broad range of products, from tablets to gaming consoles to servers and more. You will work closely with architecture, IP design, SoC implementation team, Design Verification team and physical design team to achieve first pass silicon success. You should be able to work efficiently within a team environment and drive tasks to completion, all while demonstrating excellent oral, written and interpersonal communication skills!

KEY RESPONSIBILITIES:

• Work with architecture team and production engineers to understand the product specification, DFT requirements, clock structure, power management, interconnect and AMD chiplet based infrastructure
• Define and drive DFT architecture and implementation plan for the project based on these knowledges
• Work with DFT execution team for Implementation and verification of DFT features
• Scan/Jtag/Boundary Scan insertion and ATPG pattern generation
• Memory BIST logic generation, implementation and verification
• SoC level ATPG pattern verification with gate level simulation
• Test coverage and test cost reduction analysis
• Guide DFT members to debug scan initialization sequence, scan drc and atpg simulation
• Familiar with DFT timing closure and ECO
• Post silicon support and debug to ensure successful bringup and enhance yield learning
• Help scope and analyze new design opportunities 
• Actively work on DFT methodology and process improvements
• Looking for someone who is technically hands on and a great leader

PREFERRED EXPERIENCE:

• DFT methodology/architecture and DFT verification experience (eg. IEEE1500, JTAG 1149.x, scan, memory BIST, PHY loopback, etc)
• Siemens Tessent and/or Synopsys Tetramax/DFTMAX.
• Experience with VCS simulation tool, Perl/Shell scripting and Verilog RTL design
• Prior experience and exposure to DFT timing closure is critical
• Pre-Silicon test planning & validation, engagement with design teams
• Characterization and debug of Scan/ATPG test in the new silicon designs and process technologies
• Optimization of test flows for increased quality and cost improvement
• Analysis of part failures leading to test coverage and yield improvement
• Analysis of characterization data across PVT
• Must have good communication skills and the ability to work in a worldwide team environment
• Knowledge & experience of low power concepts, clock gating, power gating is a plus
• Adept at collaboration among top-thinkers and senior architects with strong interpersonal skills to work across teams in different geographies

ACADEMIC CREDENTIALS:

• Bachelor’s or Master’s degree in related discipline preferred

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At AMD, your base pay is one part of your total rewards package.  Your base pay will depend on where your skills, qualifications, experience, and location fit into the hiring range for the position. You may be eligible for incentives based upon your role such as either an annual bonus or sales incentive. Many AMD employees have the opportunity to own shares of AMD stock, as well as a discount when purchasing AMD stock if voluntarily participating in AMD’s Employee Stock Purchase Plan. You’ll also be eligible for competitive benefits described in more detail here.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.