Sr. Hardware Development Engineer

WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

AMD together we advance_

THE ROLE:

AMD-Xilinx is seeking an Entry Level SOC Design Engineer to be part of Front End SOC Design Team of next generation Adaptable Compute Acceleration Platform device. You will take part in design and implementation of high-performance, low-power SOCs and SOC Chiplets targeting a wide range of applications as well as customer specific products. In this role, you will implement functions in RTL, integrate IP from internal and external sources, ensure quality and get design ready for synthesis. You will also contribute to definition/evolution of SOC Design methodologies and processes for future projects

LOCATION: San Jose, Onsite

THE PERSON:

• Successful candidate will have coursework in Digital Logic Design, Multi Clock-Domain designs and static timing analysis

KEY RESPONISIBILITES:

• Contribute to micro-architecture of future SOC building blocks and necessary infrastructure based on architecture, PPA, DFT, Functional Safety requirements
• RTL design and debug of functions in Verilog / System Verilog
• Integration of hard macro or soft RTL IP into SOC top level
• Execution of quality checks to improve quality of RTL/UPF/SDC deliverables
• Analysis of design metrics and making implementation choices to optimize PPA
• Targeting SOC RTL to process technology
• Work with verification and physical design teams to achieve high quality design and successful tape out
• Build automation (Python, TCL, Perl) to enhance productivity of self and team

PREFERRED EXPERIECE:

• Digital design and experience with RTL design in Verilog/System Verilog
• Understanding of DFT technologies and some experience with execution of DFT flows
• Experience with SOC tools including Spyglass, Questa CDC, Cadence Conformal, VCS simulation
• Experience in specifying timing constraints with several clock domains and modes
• Basic experience with Synopsys Design Compiler and Primetime
• TCL, Python, Perl scripting
• Version control systems such as Perforce, IC Manage or Git
• Understanding of FPGA architecture and implementation flow
• Strong verbal and written communication skills
• Ability to organize and present technical information
• Fluent in working with Linux environment

At AMD, your base pay is one part of your total rewards package.  Your base pay will depend on where your skills, qualifications, experience, and location fit into the hiring range for the position. You may be eligible for incentives based upon your role such as either an annual bonus or sales incentive. Many AMD employees have the opportunity to own shares of AMD stock, as well as a discount when purchasing AMD stock if voluntarily participating in AMD’s Employee Stock Purchase Plan. You’ll also be eligible for competitive benefits described in more detail here.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.