What are the responsibilities and job description for the Senior Design Verification Engineer SV/UVM position at Advantra Consulting Group?
Job Details
Senior Design Verification Engineer SV/UVM
Contract Long Term
Multiple roles- San francisco BayArea
Key Responsibilities- Own the verification of complex IP/subsystems using SystemVerilog and UVM methodology
- Develop robust testbenches and testplans from functional specs and architecture docs
- Build and maintain scalable UVM environments for IP, subsystem, and SoC-level simulations
- Write directed and constrained-random testcases, ensuring thorough functional and code coverage
- Perform detailed debugging and root cause analysis of failures; collaborate with RTL/design teams for quick resolution
- Execute regressions, monitor failures, and drive bug resolution
- Perform low-power simulations, validate UPF/CPF integrations, and ensure power-aware verification coverage
- Work closely with DFT, PD, and Post-Si teams to ensure end-to-end quality and signoff
- Maintain detailed documentation of testplans, environments, and verification reports for internal and external audits
Required Skills
- 5 years of hands-on verification experience with SystemVerilog and UVM
- Strong knowledge of AMBA protocols (AXI, AHB, APB)
- Experience with functional coverage, code coverage, and regressions
- Familiarity with power-aware verification (UPF/CPF) and low-power flows
- Strong debugging skills using simulators like VCS, Questa, or Xcelium
- Excellent communication and cross-functional collaboration skills
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