Principal Physical Design Engineer

Description

Invent the future with us.

Recognized by Fast Company’s 2023 100 Best Workplaces for Innovators List, Ampere is a semiconductor design company for a new era, leading the future of computing with an innovative approach to CPU design focused on high-performance, energy efficient, sustainable cloud computing.

By providing a new level of predictable performance, efficiency, and sustainability Ampere is working with leading cloud suppliers and a growing partner ecosystem to deliver cloud instances, servers and embedded/edge products that can handle the compute demands of today and tomorrow.

Join us at Ampere and work alongside a passionate and growing team — we’d love to have you apply. Come invent the future with us.

About The Role

Ampere is seeking a highly skilled and experienced candidate with proven expertise in PHY hardening, particularly in DDR and SerDes, with a focus on HBM PHY hardening.

We are looking for a self-motivated individual with a proven track record in hardening state-of-the-art PHYs and contributing to the development of cutting-edge expertise.

What You’ll Achieve

As a PHY Hardening Engineer, you will collaborate with architects, RTL designers, packaging and PCB design teams, and post-silicon validation groups. This is an exceptional opportunity to showcase your engineering skills in a dynamic, fast-paced environment that fosters innovation and operates at the forefront of technology.

High-Speed Digital Design

• Develop high-speed digital layouts, including DDR and other high-speed interfaces.
• Expertise in floor planning, bump planning, routing, power grid design, clock design/distribution, and optimization for high-speed digital circuits.
• Optimize layouts to minimize signal integrity issues, reduce power consumption, and meet timing, power, and manufacturability requirements.
• Coordinate with PHY vendors for hardening activities and deliverables.
• Estimate effort and timelines for PHY hardening tasks and provide feedback on timing/PDV.
  
  

Chip-Level Physical Design

• Perform chip-level tasks such as floor planning, partitioning, and power/clock distribution.
• Handle chip assembly and ensure seamless integration of multiple IP blocks into the top-level design.
• Proficiency in using EDA tools for chip-level physical verification (DRC, LVS, ERC).
• Collaborate with the packaging team to refine bump placement and package routing considerations.
  
  

HBM Protocol and Physical Design

• Knowledge of HBM floor planning and partitioning to achieve efficient integration with the chip.
• Design high-bandwidth memory systems, including interfaces, memory arrays, and TSV (Through-Silicon Via) structures.
• Work with architects and RTL teams to develop physical constraints and optimize HBM interfaces.
• Integrate HBM PHYs, controllers, and memory stacks into the top-level design.
  
  

Signal and Power Integrity

• Familiarity with signal and power integrity concepts in high-performance memory systems.
• Expertise in managing high-speed signals to mitigate issues like crosstalk, reflection, and signal degradation.
• Perform thermal and power integrity analysis to ensure reliable designs.
  
  

Advanced Packaging

• Experience with advanced packaging technologies, such as 2.5D/3D integration, TSV, and interposer-based designs.
• Handle micro-bump design to ensure proper alignment and minimize resistance.
• Understand the SIPI impacts of bump placement.
• In-depth knowledge of HBM memory requirements from both packaging and SIPI perspective, with the ability to adopt and implement best design practices recommended by PHY and memory vendors
  
  

Low-Power Design

• Implement and verify power intent using UPF/CPF for multi-voltage and power-gating designs.
• Collaborate with architects to refine low-power strategies like clock/power gating and voltage scaling.
  
  

Design-for-Test (DFT)

• Basic understanding of DFT structures, including scan chains, MBIST, and loopback mechanisms.
• Contribute to DFT-based timing closure activities.
  
  

About You

• Expertise in floor planning, bump planning, routing, power grid design, clock design/distribution, and optimization for high-speed digital circuits
• Experience developing high-speed digital layouts, including DDR and other high-speed interfaces
• Handling chip assembly and ensure seamless integration of multiple IP blocks into the top-level design
• Proficiency in using EDA tools for chip-level physical verification (DRC, LVS, ERC)
• Knowledge of HBM floor planning and partitioning to achieve efficient integration with the chip
• Experience designing high-bandwidth memory systems, including interfaces, memory arrays, and TSV (Through-Silicon Via) structures
• Worked with architects and RTL teams to develop physical constraints and optimize HBM interfaces
• Integrate HBM PHYs, controllers, and memory stacks into the top-level design
• Expertise in managing high-speed signals to mitigate issues like crosstalk, reflection, and signal degradation
• Experience with advanced packaging technologies, such as 2.5D/3D integration, TSV, and interposer-based designs
• Handle micro-bump design to ensure proper alignment and minimize resistance
• Understand the SIPI impacts of bump placement
• In-depth knowledge of HBM memory requirements from both packaging and SIPI perspective, with the ability to adopt and implement best design practices recommended by PHY and memory vendors
• Basic understanding of DFT structures, including scan chains, MBIST, and loopback mechanisms
• Strong communication and articulation skills are required to excel in this role
• Electrical or Computer Engineering - Bachelor's degree & 8 years of related experience; or Master's degree & 6 years; or PhD & 3 years
  
  

What We’ll Offer

At Ampere we believe in taking care of our employees and providing a competitive total rewards package that includes base pay, bonus, equity, and comprehensive benefits. The full base pay range for this role is between $146,300 and $243,800. We offer an annual bonus program tied to internal company goals and annual meritocratic equity awards that enable our employees to participate in the success of the company.

Our benefits include health, wellness, and financial programs that support employees through every stage of life, with full benefits eligibility at 20 hours per week.

Benefit Highlights Include

• Premium medical insurance, dental insurance, vision insurance, as well as income protection and a 401K retirement plan, so that you can feel secure in your health and financial future.
• Unlimited Flextime and 10 paid holidays so that you can embrace a healthy work-life balance.
• A variety of healthy snacks, energizing espresso, and refreshing drinks to keep you fueled and focused throughout the day.
  
  

And there is much more than compensation and benefits. At Ampere, we foster an inclusive culture that empowers our employees to do more and grow more. We are passionate about inventing industry leading cloud-native designs that contribute to a more sustainable future. We are excited to share more about our career opportunities with you through the interview process.

Ampere is an inclusive and equal opportunity employer and welcomes applicants from all backgrounds. All qualified applicants will receive consideration for employment without regard to race, color, national origin, citizenship, religion, age, veteran and/or military status, sex, sexual orientation, gender, gender identity, gender expression, physical or mental disability, or any other basis protected by federal, state or local law.