What are the responsibilities and job description for the Only W2/1099 Contract | Medium FW Verification Engineer | Warren, NJ - Onsite | 6+ Years position at Anagha Techno Soft?
Job Details
Only W2/1099 Contract | Medium FW Verification Engineer | Warren, NJ - Onsite | 6 Years
Role: Medium FW Verification Engineer
Experience Level: 6-8 Years
Work Model: Onsite 5 days a week from office in Warren, NJ
Onsite Location: Warren, NJ
Job Description:
As a Middle UVM SystemVerilog Verification Engineer, you will be responsible for assisting in the development and execution of test plans using Universal Verification Methodology (UVM) to validate the functionality, performance, and reliability of FPGA designs. You will work closely with senior engineers to gain hands-on experience in digital design verification.
Qualifications & Experience:
Bachelor's degree in Electrical Engineering, Computer Engineering, or related fields.
6-8 years of experience in UVM-based verification or digital design verification.
Basic understanding of SystemVerilog and Universal Verification Methodology (UVM).
Experience with C/C for verification and embedded systems.
Familiarity with scripting languages such as Python or Perl for automation.
Exposure to simulation tools such as ModelSim or QuestaSim.
Strong problem-solving and analytical skills with attention to detail.
Ability to work collaboratively in a team environment and willingness to learn.
Preferred Skills:
Knowledge of O-RAN architecture and protocols for 4G and 5G networks.
Familiarity with FPGA development and hardware description languages such as VHDL/Verilog.
Exposure to hardware/software co-verification techniques.
Understanding of wireless technologies, including 4G/5G protocols.
Knowledge of Digital Signal Processing (DSP) techniques and applications.
Job Responsibilities:
Assist in developing and implementing UVM-based verification plans for FPGA designs.
Perform functional and regression testing for digital hardware components.
Develop and maintain testbenches, test cases, and automation scripts in SystemVerilog.
Analyze test results, debug issues, and collaborate with senior engineers to resolve defects.
Ensure compliance with industry standards and customer requirements.
Document test procedures, results, and defect tracking.
Continuously learn and improve test methodologies and verification processes.
