Demo

Principal Technologist

Astera Labs
Santa Clara, CA Full Time
POSTED ON 2/19/2025
AVAILABLE BEFORE 5/16/2025

Astera Labs stands as a global leader in purpose-built connectivity solutions that harness the full potential of AI and cloud infrastructure. Our Intelligent Connectivity Platform seamlessly integrates PCIe®, CXL®, and Ethernet semiconductor-based solutions with the COSMOS software suite, offering a comprehensive set of system management and optimization tools. This results in a software-defined architecture that is both scalable and customizable. Fueled by strong partnerships with hyperscalers and the data center ecosystem, we are recognized as an innovation leader, delivering flexible and interoperable products. Explore how we are transforming modern data-driven applications at www.asteralabs.com.

Job Description

Astera Labs is seeking a Principal Silicon Technologist with a robust background in collaborating with foundries to reduce defect density, analyze critical silicon parameters, and manage all interactions between Astera Labs and the foundry. The ideal candidate will possess a proven track record of working across fabrication processes to monitor and provide insights to enhance yields and optimize design-technology co-optimization.

Responsibilities include but are not limited to : :

  • Lead technical discussions with the foundry throughout all phases of product development, from concept to high-volume manufacturing (HVM).
  • Serve as the primary point of contact for product tapeout technical communications between Astera Labs and the foundry.
  • Collaborate with the foundry on PDK library, DFM rules, defect density, yield prediction, failure analysis, yield improvement, and process correlation for all Astera Labs products.
  • Fine-tune processes to optimize power, performance, and yield.
  • Define process splits for PVT characterization according to each process node.
  • Conduct in-depth analyses of process parameters to assess their impact on product yields and performance.
  • Work alongside IP vendors, design teams, and the foundry to review and approve DFM violations.
  • Oversee foundry technology roadmaps, detailing schedules, costs, performance parameters, node selections, and technology intercepts.
  • Align specific IP feature requirements with foundry capabilities.
  • Establish and maintain quarterly reviews with the foundry.

Basic Qualifications

  • A minimum of 10 years of experience in technology development, specifically with complex SOCs, including high-speed transceivers (XCVR).
  • A strong academic and technical background in Electrical Engineering, Material Science, or a related field; a Master's degree is required, while a PhD is preferred.
  • A proven history of leading interactions with foundries across various deep sub-micron process nodes.
  • Strong statistical and data analysis skills, along with effective teamwork and communication abilities.
  • Required Experience

  • Experience in liaising between the foundry and physical design teams to evaluate design rule requirements for meeting product specifications (electrical, physical, and package).
  • Experience in holding foundries accountable for process performance and achieving agreed-upon product yield objectives.
  • Familiarity with foundry integration and device modeling.
  • A technical leadership role in at least one complete product development life cycle, from concept to production.
  • Preferred Experience

  • Experience in multi-die development, including optics.
  • Experience in qualification testing to support new product introduction (NPI), bump houses, and foundry process changes.
  • Knowledge of high-speed design techniques.
  • Experience in product cost modeling based on die size, product features, and foundry inputs.
  • The base salary range for this position is USD 160,000.00—USD 240,000.00. Your base salary will be determined based on location, experience, and the compensation of employees in similar roles.

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