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Senior Principal Digital Signal Processing Architect

Astera Labs
Alameda, CA Full Time
POSTED ON 2/20/2025
AVAILABLE BEFORE 5/17/2025

We are seeking a highly skilled and motivated Senior Principal Digital Signal Processing Architect to join our team of DSP and systems experts, digital designers, and mixed-signal design engineers. In this exciting role, you will be at the forefront of developing cutting-edge DSP SerDes for next-generation 400G per lane wireline and optical interconnects tailored for AI systems.

Your primary responsibilities will include :

  • Exploring and researching innovative modulation, equalization, and Forward Error Correction (FEC) techniques for advanced 400G per lane wireline and optical systems.
  • Designing DSP and FEC algorithms, along with bit / cycle-accurate C / C models and hardware block specifications suitable for RTL implementation.
  • Collaborating with the digital and firmware teams to enhance and deploy DSP algorithms effectively in hardware and firmware.
  • Engaging in hands-on post-silicon performance tuning and optimization to ensure high efficiency and effectiveness.
  • Developing and guiding test plans for comprehensive lab characterization.
  • Offering support to internal teams that are integrating and utilizing SerDes IP.

Basic Qualifications :

To be successful in this role, you will need :

  • A Master's degree or PhD in Computer Science, Electrical Engineering, or a related field, along with 5-10 years of experience in DSP architectures and algorithm development.
  • Required Skills :

  • Strong understanding and hands-on experience in designing adaptive DSP algorithms.
  • In-depth knowledge of digital communication and signal processing theory, including channel equalization, timing recovery, detection, and estimation.
  • Proficient programming skills in C / C , Matlab, or Python.
  • Experience in guiding and testing the transition of high-speed numerical algorithms from C / C to Verilog.
  • Additional Useful Skills :

  • Familiarity with high-speed optical and electrical channels, along with the DSP algorithms needed to mitigate their impairments.
  • Reading comprehension of Verilog RTL and ability to assist in evaluating Verilog implementations of DSP algorithms.
  • Experience with modern version control and software management practices.
  • Background in error correction methods (e.g., Reed-Solomon, BCH, soft decoding) for high-throughput, low-latency systems.
  • The base salary for this position ranges from $160,000.00 USD to $260,000.00 USD. Your specific compensation will be determined based on factors such as experience and the salary of similar positions within the company.

    Salary : $160,000 - $260,000

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