What are the responsibilities and job description for the Sr. Principal DSP Architect position at Astera Labs?
Astera Labs is seeking a highly experienced Sr. Principal DSP Architect to join their team in Sunnyvale, CA.
About the Role
The ideal candidate will have expertise in designing advanced DSP SerDes for next-generation 400G per lane wireline and optical interconnects for AI systems.
Key Responsibilities
- Research novel modulation, equalization, and FEC techniques for 400G per lane wireline and optical systems.
- Create DSP and FEC algorithms, bit/cycle-accurate C/C models, and hardware block specifications appropriate for RTL implementation.
- Work with the digital team/firmware team to optimize and implement DSP algorithms in hardware/firmware.
- Hands-on involvement in post-silicon performance tuning and optimization.
- Guide test plans for lab characterization.
- Provide support for internal customers deploying SerDes IP.
Qualifications
- Master's degree and/or PhD in Computer Science, Electrical Engineering, or related fields with 5-10 years of experience with DSP architectures and algorithm development.
- Solid understanding of and experience with designing adaptive DSP algorithms.
- Solid understanding of and experience with the practical aspects of digital communication and signal processing theory, including channel equalization, timing recovery, detection, and estimation.
- Good programming skills in C/C , Matlab or Python.
- Experience in guiding and testing the transfer of high-speed numerical algorithms from C/C to Verilog.
Additional Skills
- Familiarity with high-speed optical and electrical channels and the DSP algorithms to compensate for their impairments.
- Reading knowledge of Verilog RTL and the ability to assist with assessing Verilog implementations of DSP algorithms.
- Experienced with modern version control and software management systems.
- Experience with error correction (Reed-Solomon, BCH, soft decoding) in high-throughput, low-latency systems.
