What are the responsibilities and job description for the Formal Verification Engineer position at ATA ANALYTIQ LLC?
Job Details
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We are seeking a highly skilled Formal Verification Engineer to provide technical leadership and drive best practices in Formal Verification methodologies. In this role, you will collaborate with cross-functional teams, including Architecture and Design, to define, implement, and refine verification strategies at both block and system levels. You will be responsible for developing scalable and reusable verification environments, optimizing abstraction strategies, and ensuring comprehensive formal coverage across IP, Subsystem, and SoC domains.
(Onsite).
Key Responsibilities:
RTL Design/Verification
SystemVerilog and SVA
Any of the Scripting languages
JasperGold or VC-Formal
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