What are the responsibilities and job description for the Sr. Engineer, ASIC Design Verification position at Ayar Labs?
Sr. Engineer, ASIC Design Verification
Summary:
This role is responsible for pre-Si verification and validation of complex SoCs with both high-speed custom and digital blocks. You will work in a dynamic startup environment as part of a small IC design team. The ideal candidate is a hands-on self-starter who can craft design specifications, verification suites and test-benches based on input from colleagues, customers, and industry and who can effectively manage his or her own time to take projects to completion with limited supervision and guidance.
Essential Functions:
Summary:
This role is responsible for pre-Si verification and validation of complex SoCs with both high-speed custom and digital blocks. You will work in a dynamic startup environment as part of a small IC design team. The ideal candidate is a hands-on self-starter who can craft design specifications, verification suites and test-benches based on input from colleagues, customers, and industry and who can effectively manage his or her own time to take projects to completion with limited supervision and guidance.
Essential Functions:
- Develop verification methodology and testbenches for digital and mixed-signal blocks
- Test plan, coverage analysis and closure for parallel link and SerDes IP blocks and on-chip interconnects
- Design and contribute to design for test (DFT) methodologies
Basic Qualifications:
- BS, MS in Electrical Engineering, Computer Engineering or equivalent
- 2 years of ASIC verification experience in industry
- 2 years of System Verilog, UVM testbench development for design verification of complex digital and PHY blocks (in AMS and WREAL modeling verification)
- 2 years of pre-synthesis, and post- place-and-route functional verification (NCSIM, VCS, ModelSim)
- 2 years of scripting and/or programming skills
Preferred Qualifications:
- Experience working on digital designs with multiple clock domains and clock dividers
- Experience in verification of SerDes IP block interfaces in a complex SoC fabric environment
- Experience in verification of the PCS, PMA SerDes layers and internal SerDes digital backends
- Experience with verification of HBM memory interfaces (PHY and controller)
- Experience in formal model equivalence checking tools and verification methodology
- Programming experience in Python
Pay Range is $120K to $165K
Recruiters:
Principals only. We are not accepting resumes from recruiters for this position. Remuneration for recruiting activities is only applicable subject to a signed and executed agreement between the parties. Please don’t send candidates to Ayar Labs, and please don't contact our managers or employees.
About Ayar Labs:
At Ayar Labs we’re about to revolutionize computing by moving data with light. We’re unleashing processing power for artificial intelligence, high performance computing, cloud and telecommunications by removing the bottlenecks created by today’s electrical I/O -- making it possible to continue scaling computing system performance. Ayar Labs is the first to deliver an optical I/O solution that combines in-package optical I/O chiplets and multi-wavelength remote light sources to replace traditional electrical I/O. This silicon photonics-based I/O solution enables chips to communicate with each other from millimeters to kilometers, to deliver orders of magnitude improvements in latency, bandwidth density, and power consumption.
With our strong collaborations with industry leaders and government, our deep ties to MIT and UC Berkeley, and our commitment to hiring the best engineers in photonics and electronics, joining our team gives you the opportunity to collaborate with renowned experts on challenging, paradigm-shifting work.
We are passionate about delivering in-package optical I/O at scale, leveraging the strength of our patent portfolio and our team of leading interdisciplinary experts. We believe that deep cross-collaboration between teams facilitated by honest, open debate is the best way to drive innovation and achieve big wins. Join our team and experience the possibilities.
Resources:
With our strong collaborations with industry leaders and government, our deep ties to MIT and UC Berkeley, and our commitment to hiring the best engineers in photonics and electronics, joining our team gives you the opportunity to collaborate with renowned experts on challenging, paradigm-shifting work.
We are passionate about delivering in-package optical I/O at scale, leveraging the strength of our patent portfolio and our team of leading interdisciplinary experts. We believe that deep cross-collaboration between teams facilitated by honest, open debate is the best way to drive innovation and achieve big wins. Join our team and experience the possibilities.
Resources:
- Executives from Intel and GLOBALFOUNDRIES share their thoughts on Ayar Labs and the promise of in-package optical I/O (video)
- Ayar Labs in the News and Recent announcements
- LinkedIn and Twitter
Ayar Labs is an Affirmative Action/Equal Opportunity Employer and is strongly committed to all policies which will afford equal opportunity employment to all qualified persons without regard to age, national origin, race, ethnicity, creed, gender, disability, veteran status, or any other characteristic protected by law.
Salary : $120,000 - $165,000
