What are the responsibilities and job description for the Sr. Manager, ASIC Engineering position at Ayar Labs?
Sr. Manager, ASIC Engineering
GENERAL DESCRIPTION
The Sr. Manager of ASIC Engineering will be responsible for leading design team execution from concept to silicon for complex SoCs with both high-speed custom and digital blocks. As a Sr. Manager, you will be expected to lead a team within the broader ASIC Engineering organization and to work closely with the Analog Mixed-Signal and Photonics design teams to bring tapeouts to completion. The ideal candidate will bring strong interpersonal and communication skills while having deep technical expertise in multiple aspects of the ASIC design process. In addition, the candidate will be expected to manage his or her own time and that of the team to take projects to completion with limited supervision and guidance.
Essential Functions:
GENERAL DESCRIPTION
The Sr. Manager of ASIC Engineering will be responsible for leading design team execution from concept to silicon for complex SoCs with both high-speed custom and digital blocks. As a Sr. Manager, you will be expected to lead a team within the broader ASIC Engineering organization and to work closely with the Analog Mixed-Signal and Photonics design teams to bring tapeouts to completion. The ideal candidate will bring strong interpersonal and communication skills while having deep technical expertise in multiple aspects of the ASIC design process. In addition, the candidate will be expected to manage his or her own time and that of the team to take projects to completion with limited supervision and guidance.
Essential Functions:
- Lead, motivate, and grow a team of engineers spanning all aspects of ASIC design from RTL to GDS
- Conduct code, constraints, and flow reviews to ensure quality of all design inputs and components and best known methods
- Create and maintain technical documentation and checklists
- Deliver completed blocks on-time and on-schedule
- Work efficiently with both local and remote employees across different time zones and geographies
Basic Qualifications:
- BS or MS in Electrical Engineering, Computer Engineering, or related fields
- 8 years of experience in ASIC design
- 2 years of experience leading projects and teams through tapeout cycles
- Excited about working on breakthrough technologies
- History of technical leadership, collaboration, and cross-functional influence, mentorship to peers
- History of demonstrating deep problem solving resolve and diligence in root causing issues
- Strong proficiency in Verilog for RTL design
- Strong proficiency in timing methodology and understanding of timing analysis
- Strong proficiency in backend ASIC flows: synthesis (Genus, Design Compiler), place and route (Innovus, ICC)
- Proficiency in scripting or programming languages
Preferred Qualifications:
- Knowledge of high-speed SerDes or SerDes components
- Experience in DFT methodologies and flows such as scan insertion, BIST, ATPG, etc.
- Experience working on digital designs with multiple clock domains, clock dividers, and custom analog components
- Experience with physical sign-off (Calibre DRC, LVS) tools
- Working knowledge integrating custom blocks in a digital-top flow (LEF, lib, etc.)
- Working knowledge of the Cadence Virtuoso design environment for manual schematic entry, layout, and simulation
- Performed silicon bring-up, debug, and evaluation
- Programming experience in Python
Pay Range is $175K to $230K
At Ayar Labs we are lighting up electronics for a brighter future. With our deep ties to MIT and UC Berkeley, and our commitment to hiring the best engineers in photonics and electronics, joining our team gives you the opportunity to collaborate with brilliant people on challenging, paradigm-shifting work. Our optical I/O technology removes the bottlenecks created by today’s electrical I/O, making it possible to continue the computing system performance scaling that Moore’s Law enabled until now. We have a commitment to win big in the marketplace based on the strengths of our technology, and we approach everything with an eye to massive scalability. We believe that deep cross-collaboration between teams facilitated by honest, open debate is the best way to achieve big wins, leveraging our patent portfolio which promises products that deliver orders of magnitude improvements in latency, bandwidth density, and power consumption. We offer a comprehensive benefits plan designed to keep our team healthy and happy.
Resources
- Executives from Intel and GLOBALFOUNDRIES share their thoughts on Ayar Labs and the promise of in-package optical I/O (video)
- Ayar Labs in the News and Recent announcements
- LinkedIn and Twitter
Ayar Labs is an Affirmative Action/Equal Opportunity Employer and is strongly committed to all policies which will afford equal opportunity employment to all qualified persons without regard to age, national origin, race, ethnicity, creed, gender, disability, veteran status, or any other characteristic protected by law.
Salary : $175,000 - $230,000
