Wireless PHY ASIC Design Engineer

Our client, a high-tech company based in San Jose, CA, is seeking an experienced Wireless PHY ASIC Design Engineer.

**Candidates must be U.S. citizen or Green Card holder.**

This is a long-term (12 months ) contract role. Our company will hire a W2 employee, or for senior-level candidates, who own their own business, we will consider working CC.

No visa sponsorship or 3rd parties will be considered for this role.

JOB SUMMARY

Work on the latest WLAN technology and product development. Successful candidates will be participating in the design of leading edge ASICs for Wireless Connectivity SoC platform.

RESPONSIBILITIES AND DUTIES

This position is responsible for:

PHY ASIC design engineer is responsible for the design and implementation of WiFi Baseband modem. Duties include, but are not limited to:

·       Architect and develop state of the art microarchitecture of various processing blocks in WiFi PHY hardware based on signal processing algorithm, including baseband modem design, interface design to RF subsystem, MAC subsystem and SoC.

·       Implement and deliver PHY RTL design according to fixed-point reference model, assist the synthesis, timing and power analysis.

·       Develop unit-level verification and support bi-true verification with reference model, work with DV engineer for integrated-level verification.

·       Lint, CDC check. Assist in all different level of ASIC simulation.

·       Support FPGA prototyping or SoC Lab validation

KNOWLEDGE, SKILLS, & COMPETENCY REQUIREMENTS

Competency is based on education, training, skills, and experience. In order to successfully perform this job, an individual must demonstrate the following knowledge, skills, and competencies:

·       Knowledge of 802.11 (11b/a/g/n/ax/ax/be) WiFi PHY baseband spec is desired

·       Knowledge of wireless baseband DSP algorithm and ASIC implementation.

·       Must have experience of fixed point digital design and RTL implementation.

·       Familiar with ASIC flow from micro-architecture development, RTL coding, CRC/RDC, power analysis, Synthesis and STA and timing closure, to final tape-out and production support.

·       Expertise in verification and validation of signal processing ASICs is required.

·       Desired PHY ASIC implementation experience include FEC Decoder, Beam-Forming, MIMO Channel Estimation and equalization, Channel Smoothing, Noise Whitening, FFT, DFE and digital filters.

·       Experience of low power design

The following traits are highly valued:

·       Knowledge of wireless communication system such as WiFi, Bluetooth, UWB, 4G LTE and 5G NR is a plus

·       Advanced wireless communication techniques including MIMO OFDM/OFDMA system design, signal acquisition, synchronization, and equalization, advanced error correction techniques is a plus.

·       Experience of SoC architecture, on-chip SoC bus protocol, framers/deframers and data movers, CPU/DSP architectures and embedded subsystems is a plus.

·       Familiarity with RFIC architecture is a plus.

EDUCATION & EXPERIENCE

·       Minimum years of applicable work experience 7 years

·       BS/MS/Ph.D. in EE or related