Demo

Senior Hardware Engineer

Blue Chip Talent
Palo Alto, CA Full Time
POSTED ON 4/26/2025
AVAILABLE BEFORE 5/23/2025

Job Description :

We are looking for an experienced Senior Hardware Engineer to contribute to all design phases of high-performance System on Chip (SoC) development. You will work across block, subchip, and full-chip levels, from RTL to GDSII. This position involves collaborating with a diverse team of engineers, including Foundry Process Engineers, SoC Architects, Microarchitecture Teams, Packaging, Signal Integrity, and Power Integrity teams, to drive the physical design aspects of the SoC. Your role will ensure a successful tapeout and production of silicon.

Key Responsibilities :

  • Perform subchip and block-level place and route, ensuring design meets performance, power, and area targets.
  • Lead and execute full-chip SoC integration activities, including : Die size optimization, Floorplanning, Hard IP integration, Partitioning, Chip-level clock planning, Bump placement / RDL routing, Power grid generation, Full-chip STA timing, DFT strategy planning, Final physical verification.
  • Analyze and resolve timing, power, and congestion issues in collaboration with the front-end design team.
  • Define and support EM-IR sign-off requirements and methodologies.
  • Conduct voltage drop analysis using tools like Redhawk or Redhawk-SC, and debug EM / IR issues to ensure successful tapeout.
  • Develop and support Chip-package-Co-Analysis (CPA) and Chip-Power-Model (CPM) for package & die co-design analysis.
  • Provide hands-on experience and leadership in static and dynamic analysis, including thermal, electro-migration, peak current, di / dt, and effective resistance analysis.
  • Ensure timing analysis, power analysis, and physical verification (DRC / LVS) are completed effectively.

Key Qualifications :

  • Extensive experience in physical design, including both block-level and subchip-level design, with full-chip level experience considered a plus.
  • Deep knowledge of physical design concepts, including : Physical-aware synthesis, Floorplanning, Clock tree implementation, Routing, STA timing signoff, Chip-finishing
  • Proficient understanding of basic SoC architecture, with the ability to collaborate with the front-end design team on timing, congestion, and power issues.
  • In-depth knowledge of the design flow from RTL to GDSII.
  • Strong familiarity with EM-IR sign-off requirements and methodologies.
  • Proficiency in using EDA tools such as Synopsys (or Cadence) for PPA optimization.
  • Strong scripting skills in languages such as Perl and TCL.
  • Solid background in EM-IR fundamentals, voltage drop analysis, and debugging skills for finding root causes of voltage drop and EM issues.
  • Excellent analytical aptitude with exceptional attention to detail.
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