Senior Physical Design Engineer

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Blue Chip Talent is looking for a Senior Physical Design Engineer, in Palo Alto, CA to will lead critical stages of the physical design process for high-performance SoCs, working from RTL to GDSII. Collaborate with cross-functional teams to ensure successful tapeouts and production silicon.

Key Qualifications:

• Extensive experience in physical design at block, subchip, and full-chip levels.
• Expertise in synthesis, floorplanning, clock tree implementation, routing, STA timing signoff, and chip-finishing.
• Strong knowledge of SoC architecture and RTL-to-GDSII flow.
• Proficiency in EDA tools (Synopsys, Cadence) and scripting (Perl, Tcl).
• Hands-on experience with EM-IR signoff and PPA optimization.

Responsibilities:

• Perform place-and-route tasks, ensuring PPA goals.
• Lead full-chip integration, including die size optimization, floorplanning, and verification.
• Conduct timing, power, and physical verification (DRC/LVS).
• Define UPF specifications and execute EM-IR signoff processes.
• Perform thermal, electro-migration, and voltage drop analyses.
• Support Chip-Package Co-Analysis (CPA) and Chip-Power-Model (CPM).

Additional Responsibilities:

• Collaborate with Foundry Engineers and cross-functional teams to define design parameters.
• Automate EDA flows for floorplanning, routing, and verification.
• Align floorplans with packaging, board layout, and power delivery.
• Ensure robust power distribution and clocking architecture.

Other Qualifications:

• 15–20 years of semiconductor experience with proven silicon delivery.
• Expertise in defining complex SoCs across technology nodes.
• BS/MS/PhD in Electrical/Computer Engineering.
• Knowledge of CPU architecture and multi-SoC systems is a plus.
• Familiarity with machine learning algorithms is desirable.

This role offers the chance to contribute to cutting-edge SoC designs and collaborate with industry-leading teams.