What are the responsibilities and job description for the Digital Design (RTL) Engineer position at BLYK Engineering Services?
Key Responsibilities:
Develop RTL designs using Verilog/System Verilog.
Create micro-architecture and support SoC integration.
Perform linting, synthesis, static checks, and low power design.
#Skills and #Preferred:
10 years in RTL design, Verilog/System Verilog.
Experience in design, integration, and verification.
Familiarity with EDA tools (Synopsys, Cadence), scripting (Python).
Experience with DMA, memory controllers, MIPI, AMBA.
