What are the responsibilities and job description for the Internship - Design Engineering position at Cadence Design Systems?
This is an exciting new opportunity for a Design Engineering Intern at Cadence : The Cadence Tensilica CPU Processor Team is experiencing rapid growth, with industry-leading processor cores and DSPs gaining widespread adoption. These highly configurable and extensible processor cores are designed to meet the evolving demands of intelligent IoT devices and edge ML / AI applications. Cadence's processors are already driving advancements in Audio, Speech, AR / VR, ADAS, Vision, and Imaging applications for many of the top chip and system companies. Currently, Cadence ships an impressive 8 billion processor cores annually and is expanding into intelligent system design and development.The Cadence Tensilica CPU Processor Team is seeking interns to join its RandD teams in San Jose and Austin. This is a unique opportunity to gain experience as a Graduate Engineer at a global leader in computational software, semiconductor design IP, and system verification hardware. Cadence collaborates with the world’s most innovative companies, enabling them to develop cutting-edge electronic products ranging from chips and boards to complete systems across a variety of dynamic markets, including hyperscale computing, 5G communications, automotive, mobile, aerospace, consumer, industrial, and healthcare.Interns will join the esteemed Processor Team, where they can make a tangible impact. The Design Engineering Intern role falls into one of the following two categories : (a) Working as part of the Logic Design Team for Xtensa processors. Responsibilities include RTL implementation of microprocessor cores, multiprocessor sub-systems, and their peripherals. Tasks involve implementing micro-architecture in Verilog RTL, simulating and debugging functions, and executing synthesis, place and route, and other Electronic Design Automation (EDA) scripts to achieve timing, area, and power goals. Additionally, the intern will assist in developing test plans, writing functional diagnostics, debugging failures, and analyzing coverage data while collaborating closely with Design Verification and EDA teams.(b) Working as part of the Design Verification Team for Xtensa processors. Responsibilities include verifying microprocessor cores, multiprocessor sub-systems, and their peripherals. Tasks involve assisting in developing test plans, writing functional assembly diagnostics, creating UVM / SVA monitors, debugging failures, and analyzing coverage data. This role also requires close collaboration with RTL Design and EDA teams. Position Requirements : Currently pursuing an MS / BS in Electrical Engineering, Computer Engineering, or a related field.Strong understanding of Digital Design and / or Design Verification fundamentals.Proficiency in automation tools such as Tcl, Perl, and shell scripting.Excellent verbal and written communication skills.Familiarity with design automation tools is a plus. At Cadence, meaningful work is at the forefront. Join the team and help solve complex challenges that others cannot.
