What are the responsibilities and job description for the Functional Verification Engineer position at Canvendor?
Design Verification Engineer (Functional Verification).
Location : Bay Area, CA.
Experience : 8 Years.
Seeking an experienced Design Verification Engineer with 8 years in functional verification of digital designs. The ideal candidate will have proficiency in SystemVerilog and UVM, knowledge of Verilog or VHDL, and extensive experience with high-speed interfaces such as Ethernet, PCIe, DDR, UCIE.
Roles and responsibilities :
- Must have 8 years of experience in functional verification of digital designs.
- Develop and execute comprehensive verification plans for digital designs.
- Create and maintain testbenches, test cases, and verification environments.
- Implement directed and constrained-random test methodologies.
- Perform coverage analysis and drive verification closure.
- Ensure compliance with industry standards for high-speed interfaces.
- Collaborate with design and system engineering teams.
- Proficient in SystemVerilog and UVM .
- Knowledge of Verilog or VHDL .
- Extensive experience with high-speed interfaces (e.g., Ethernet, PCIe, DDR, UCIE) is essential.
- Familiarity with industry-standard verification tools (e.g., VCS, Questa, Synopsys, Cadence).
- Experience with scripting languages (e.g., Python, Perl).
- Strong debugging and problem-solving skills.
- Excellent communication and teamwork skills.
