Analog/Mixed - Signal (AMS) Design Verification (DV) Engineer

The Analog/Mixed-Signal (AMS) Design Verification (DV) Engineer will be responsible for developing SystemVerilog-based AMS models, creating UVM testbenches, and verifying analog and mixed-signal designs. This role will involve collaborating with circuit designers and layout engineers to ensure functionality, timing, and performance meet specifications.

Key Responsibilities:

Analog/Mixed-Signal Modeling & Verification:

• Extract modeling specifications from circuit designers.
• Develop analog/mixed-signal (AMS) models in SystemVerilog for verification.
• Create and maintain UVM testbenches for AMS verification.
• Develop test cases, run simulations, and debug issues in behavioral models.
• Work closely with layout engineers to develop timing models for circuit validation.
• Identify design anomalies and determine if they are caused by errors in specifications, models, testbenches, or circuits.
• Support integration of AMS models into larger system models.

Required Skills & Qualifications:

Technical Expertise:

• Strong knowledge of SystemVerilog RTL coding, including state machines, adders, multipliers, and combinatorial logic.
• Experience in AMS modeling and writing behavioral Verilog code for analog circuits (e.g., bandgap, PLL, amplifiers, filters).
• Hands-on experience with UVM testbench development and writing test cases.
• Familiarity with digital design for mixed-signal control loops and designing Verilog/Verilog-A models for controlling analog circuits.
• Deep understanding of constraints for mixed-signal designs, including multiple clock domains and clock gating.
• Strong knowledge of timing closure, static timing analysis tools, and constraint development.
• Experience with scan chain vector generation and verification.

Education & Experience:

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• 5 years of Analog/Mixed-Signal Design Verification (AMS DV) experience.

Preferred Qualifications:

• Experience with Cadence AMS Designer, Mentor Questa ADMS, or Synopsys VCS AMS for AMS simulations.
• Hands-on experience with SPICE, Verilog-A, or behavioral modeling tools.
• Knowledge of assertion-based verification techniques for AMS designs.
• Experience with power-aware verification methodologies for mixed-signal SoCs.

Skills Summary:

• Core Expertise: Analog/Mixed-Signal Design Verification, SystemVerilog, UVM, AMS modeling.
• Simulation Tools: AMS Designer, Questa ADMS, Synopsys VCS AMS.
• Digital & Analog Circuit Modeling: Verilog-A, Verilog-AMS, Mixed-Signal Control Loops.
• Verification Techniques: Static Timing Analysis, Multiple Clock Domain Handling, Scan Chain Vector Generation.
• Soft Skills: Problem-Solving, Debugging, Cross-Team Collaboration, Documentation.

This remote role is ideal for AMS verification engineers with expertise in SystemVerilog, AMS modeling, and UVM-based testbench development, focusing on high-performance analog and mixed-signal circuit verification.

The Analog/Mixed-Signal (AMS) Design Verification (DV) Engineer will be responsible for developing SystemVerilog-based AMS models, creating UVM testbenches, and verifying analog and mixed-signal designs. This role will involve collaborating with circuit designers and layout engineers to ensure functionality, timing, and performance meet specifications.

Job Description:

Title:

• Analog/Mixed-Signal (AMS) Design Verification (DV) Engineer

Location:

• Remote

Key Responsibilities:

Analog/Mixed-Signal Modeling & Verification:

• Extract modeling specifications from circuit designers.
• Develop analog/mixed-signal (AMS) models in SystemVerilog for verification.
• Create and maintain UVM testbenches for AMS verification.
• Develop test cases, run simulations, and debug issues in behavioral models.
• Work closely with layout engineers to develop timing models for circuit validation.
• Identify design anomalies and determine if they are caused by errors in specifications, models, testbenches, or circuits.
• Support integration of AMS models into larger system models.

Required Skills & Qualifications:

Technical Expertise:

• Strong knowledge of SystemVerilog RTL coding, including state machines, adders, multipliers, and combinatorial logic.
• Experience in AMS modeling and writing behavioral Verilog code for analog circuits (e.g., bandgap, PLL, amplifiers, filters).
• Hands-on experience with UVM testbench development and writing test cases.
• Familiarity with digital design for mixed-signal control loops and designing Verilog/Verilog-A models for controlling analog circuits.
• Deep understanding of constraints for mixed-signal designs, including multiple clock domains and clock gating.
• Strong knowledge of timing closure, static timing analysis tools, and constraint development.
• Experience with scan chain vector generation and verification.

Education & Experience:

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• 5 years of Analog/Mixed-Signal Design Verification (AMS DV) experience.

Preferred Qualifications:

• Experience with Cadence AMS Designer, Mentor Questa ADMS, or Synopsys VCS AMS for AMS simulations.
• Hands-on experience with SPICE, Verilog-A, or behavioral modeling tools.
• Knowledge of assertion-based verification techniques for AMS designs.
• Experience with power-aware verification methodologies for mixed-signal SoCs.

Skills Summary:

• Core Expertise: Analog/Mixed-Signal Design Verification, SystemVerilog, UVM, AMS modeling.
• Simulation Tools: AMS Designer, Questa ADMS, Synopsys VCS AMS.
• Digital & Analog Circuit Modeling: Verilog-A, Verilog-AMS, Mixed-Signal Control Loops.
• Verification Techniques: Static Timing Analysis, Multiple Clock Domain Handling, Scan Chain Vector Generation.
• Soft Skills: Problem-Solving, Debugging, Cross-Team Collaboration, Documentation.

This remote role is ideal for AMS verification engineers with expertise in SystemVerilog, AMS modeling, and UVM-based testbench development, focusing on high-performance analog and mixed-signal circuit verification.