ASIC Physical Design Engineer

Job Responsibility

• Chip level floor planning, partitioning, timing budget generation, power planning, top-level PnR, CTS, block integration and ECO generation.
• Expertise in timing closure (STA) of high frequency blocks
• Handling blocks of high instance counts and complex designs ? 1M instances and clock frequencies about 1 GHz
• Experience with low power implementation and signoff, power gating, multiple voltage rails, UPF knowledge.
• Experience in Block-level and Full-chip integration.
• Knowledge of signoff closure ? Timing with SI and OCV, Power, IR and Physical Verification at both block and chip level
• Understanding constraints and fixing design/timing techniques
• Block level implementation from netlist to GDS
• Understanding SI prevention, fixing methodology and implementation
• Proficient in layout edit techniques
• Proficient in Synopsys Fusion Compiler, ICC/ICC2, PTSi, and Cadence EDA Tool Suite
• Experience in Design Automation and UNIX system.
• Experience in Tcl/Tk, PERL, Python is a plus.

Desired Skills & Experience:

• Must possess 8 years of hands-on experience in handling block/chip level implementation from Netlist to GDSII
• Must possess hands on experience in timing closure and physical verification closure
• Must have handled blocks of sizes 1M instances and above at frequencies higher than 1GHz
• Experience in handling lower tech nodes that include 3nm, 5nm, 7nm, 10nm, 16nm, etc.
• Must have hands on tape-out experience in lower tech nodes in any of the tools mentioned such ICC/ICC2, Fusion Compiler or Cadence APR tools.
• Must have the ability to think on the spot for quick solutions and work-around at the time of tape-out to hit the schedule on time
• Must possess excellent scripting skills ? TCL or Perl or Python
• Experience in Synthesis and Formal is a plus
• Excellent verbal and written communication skills are required.
• Must possess excellent debug skills, analytical skills, and the ability to work independently.
• Must be highly motivated and possess excellent team spirit
• Synopsys Or Cadence EDA Tool Suite, STA, PrimeTime-Si, PNR,
• Synopsys Or Cadence EDA Tool Suite, STA, PrimeTime-Si, PNR, Python/TCL

The pay range that the employer in good faith reasonably expects to pay for this position is $45.30/hour - $70.79/hour. Our benefits include medical, dental, vision and retirement benefits. Applications will be accepted on an ongoing basis.

Tundra Technical Solutions is among North America’s leading providers of Staffing and Consulting Services. Our success and our clients’ success are built on a foundation of service excellence. We are an equal opportunity employer, and we do not discriminate on the basis of race, religion, color, national origin, sex, sexual orientation, age, veteran status, disability, genetic information, or other applicable legally protected characteristic. Qualified applicants with arrest or conviction records will be considered for employment in accordance with applicable law, including the Los Angeles County Fair Chance Ordinance for Employers and the California Fair Chance Act. Unincorporated LA County workers: we reasonably believe that criminal history may have a direct, adverse and negative relationship with the following job duties, potentially resulting in the withdrawal of a conditional offer of employment: client provided property, including hardware (both of which may include data) entrusted to you from theft, loss or damage; return all portable client computer hardware in your possession (including the data contained therein) upon completion of the assignment, and; maintain the confidentiality of client proprietary, confidential, or non-public information. In addition, job duties require access to secure and protected client information technology systems and related data security obligations.

Salary : $45 - $71