Design Verification Engineer

The Design Verification Engineer will be responsible for ensuring first-pass success in ASIC development cycles, with expertise in SystemVerilog/UVM, ARM-based SoC verification, and AXI/AHB/APB protocols. The ideal candidate will have strong debugging, scripting, and functional verification skills, collaborating with cross-functional teams to ensure high-quality design implementation.

SoC & Subsystem Verification:

• Define and implement SoC verification plans and develop UVM-based testbenches for sub-system/SoC-level verification.
• Develop and execute functional tests based on the verification test plan.
• Ensure concurrency and memory access verification within ARM-based SoCs.
• Conduct integration testing for subsystems with multiple processors (ARM/RISC) and NOC.

Debugging & Root Cause Analysis:

• Debug, root-cause, and resolve functional failures in collaboration with the design team.
• Drive design verification closure using defined test plan, functional, and code coverage metrics.
• Work on AXI/AHB/APB protocol verification and ensure top-level functionalities.

EDA Tools & Scripting:

• Utilize Synopsys, Cadence, and Mentor Graphics tools for ASIC/SoC verification.
• Automate verification tasks using Python, TCL, Perl, or Shell scripting.
• Implement functional coverage and assertions to improve verification quality.

Cross-Functional Collaboration:

• Work closely with design, emulation, modeling, and silicon validation teams.
• Optimize verification methodologies using the latest industry tools and techniques.
• Develop continuous improvements for design verification flows.

Required Qualifications:

• 8 to 10 years of experience in ASIC/SoC Design Verification.
• Bachelor’s degree in Computer Science, Computer Engineering, or related field.
• Expertise in SystemVerilog UVM methodology, assertions, and functional coverage.
• Experience in ARM-based SoC verification.
• Hands-on experience with AXI, AHB, and APB protocols.
• Strong knowledge of EDA tools and scripting languages (Python, TCL, Perl, Shell).
• Experience with C/C for writing and debugging processor-based tests.

Preferred Qualifications:

• Experience verifying multi-core GPU/CPU architectures.
• Strong background in high-speed interface protocols like PCIe, DDR, Ethernet.
• Knowledge of revision control systems (Git, Mercurial, SVN).
• Understanding of AI/ML, video, and networking ASIC verification.
• Hands-on experience with formal verification, emulation, and coverage-driven verification.

Skills Summary:

• Core Expertise: SystemVerilog UVM, SoC/Subsystem Verification, Functional Testing.
• EDA Tools: Synopsys, Cadence, Mentor Graphics.
• Scripting & Automation: Python, TCL, Perl, Shell.
• High-Speed Interfaces: AXI, AHB, APB, PCIe, DDR, Ethernet.
• Debugging & Analysis: Waveform analysis, Coverage Metrics, Root Cause Analysis.
• Soft Skills: Collaboration, Problem-Solving, Communication.

This role is ideal for a highly skilled verification engineer looking to optimize SoC verification methodologies and drive innovation in ASIC development.

The pay range that the employer in good faith reasonably expects to pay for this position is $48.54/hour - $75.85/hour. Our benefits include medical, dental, vision and retirement benefits. Applications will be accepted on an ongoing basis. Tundra Technical Solutions is among North America’s leading providers of Staffing and Consulting Services. Our success and our clients’ success are built on a foundation of service excellence. We are an equal opportunity employer, and we do not discriminate on the basis of race, religion, color, national origin, sex, sexual orientation, age, veteran status, disability, genetic information, or other applicable legally protected characteristic. Qualified applicants with arrest or conviction records will be considered for employment in accordance with applicable law, including the Los Angeles County Fair Chance Ordinance for Employers and the California Fair Chance Act. Unincorporated LA County workers: we reasonably believe that criminal history may have a direct, adverse and negative relationship with the following job duties, potentially resulting in the withdrawal of a conditional offer of employment: client provided property, including hardware (both of which may include data) entrusted to you from theft, loss or damage; return all portable client computer hardware in your possession (including the data contained therein) upon completion of the assignment, and; maintain the confidentiality of client proprietary, confidential, or non-public information. In addition, job duties require access to secure and protected client information technology systems and related data security obligations.

Salary : $49 - $76