What are the responsibilities and job description for the Senior E/E & Semiconductor Engineer - CAD/EDA – Silicon Design/Verification Infrastructure Engineer position at Capgemini?
Senior E / E & Semiconductor Engineer - CAD / EDA – Silicon Design / Verification Infrastructure Engineer-078199
Description
Job Summary :
We are seeking a skilled CAD Infrastructure Lead to support our ASIC design team. The ideal candidate will be responsible for developing and maintaining the CAD infrastructure, ensuring efficient design workflows, and supporting the design and verification of ASICs.
Key Responsibilities :
- Develop and Maintain CAD Infrastructure : Create and manage CAD tools and environments to support ASIC design and verification processes.
- Support Design Teams : Provide technical support to design teams, helping them utilize CAD tools effectively.
- Automation and Scripting : Develop scripts and automation tools to streamline design workflows! and improve productivity.
- Tool Integration : Integrate various EDA (Electronic Design Automation) tools to ensure seamless operation and data flow.
- Design Verification : Assist in the verification of ASIC designs, ensuring they meet performance and quality standards!
- Documentation : Maintain comprehensive documentation of CAD processes, tools, and workflows.
- Collaboration : Work closely with multi-functional teams, including design, verification, and physical implementation teams, to address design challenges and optimize workflows.
- Lead a team of infrastructure engineers in US / India
Required Skills :
Qualifications :
Life at Capgemini
Capgemini supports all aspects of your well-being throughout the changing stages of your life and career. For eligible employees, we offer :
Salary : $88,800 - $166,398
