What are the responsibilities and job description for the Senior E/E & Semiconductor Engineer - Physical Design Engineer position at Capgemini?
Senior E / E & Semiconductor Engineer - Physical Design Engineer-078399
Description
Job Description
Job Responsibility
- Chip level floor planning, partitioning, timing budget generation, power planning, top-level PnR, CTS, block integration and ECO generation.
- Expertise in timing closure (STA) of high frequency blocks
- Handling blocks of high instance counts and complex designs – 1M instances and clock frequencies about 1 GHz
- Experience with low power implementation and signoff, power gating, multiple voltage rails, UPF knowledge.
- Experience in Block-level and Full-chip integration.
- Knowledge of signoff closure – Timing with SI and OCV, Power, IR and Physical Verification at both block and chip level
- Understanding constraints and fixing design / timing techniques
- Block level implementation from netlist to GDS
- Understanding SI prevention, fixing methodology and implementation
- Proficient in layout edit techniques
- Proficient in Synopsys Fusion Compiler, ICC / ICC2, Cadence Innovus, PTSi
- Experience in Design Automation and UNIX system.
- Experience in Tcl / Tk, PERL, Python is a plus.
Desired Skills & Experience :
Verilog / VHDL (Priority : 1)
Synopsys / Cadence EDA Tools (Priority : 1)
Primetime (Priority : 1)
ICC2 (Priority : 1)
Fusion Compiler (Priority : 1)
Python
Perl
Virtuoso
Life at Capgemini
Capgemini supports all aspects of your well-being throughout the changing stages of your life and career. For eligible employees, we offer :
Salary : $88,800 - $187,740
