What are the responsibilities and job description for the SoC Design Verification Engineer (contract) position at Capgemini?
The SOC Design Verification Engineer will be responsible for defining and implementing SoC verification plans, developing UVM-based verification environments, and debugging functional failures in complex ASIC designs. The ideal candidate should have strong expertise in SystemVerilog UVM, scripting for automation, and industry-standard EDA verification tools. The role requires hands-on experience with high-speed interfaces, emulation, and verification for AI/ML, video, and networking applications.
Design Verification & Test Planning
Design Verification & Test Planning
- Define and implement SoC verification plans for complex ASIC designs.
- Develop functional tests based on the verification test plan.
- Build verification test benches to enable sub-system/SoC level verification.
- Debug, root-cause, and resolve functional failures in the design.
- Collaborate with design, model, and emulation teams to ensure high design quality.
- Drive Design Verification to closure using functional and code coverage metrics.
- Utilize Synopsys and Cadence EDA design/verification tools for functional verification.
- Develop automation scripts using Python, TCL, Perl, or Shell scripting.
- Work with design, emulation, and silicon validation teams to drive verification improvements.
- Implement best-in-class UVM verification methodologies.
- Ensure design verification aligns with industry standards for data-center applications, AI/ML, networking, and video processing.
- Develop and drive continuous design verification improvements using the latest industry methodologies and technologies.
- Contribute to verification automation and build scalable test frameworks.
- 8 to 10 years of experience in ASIC/SoC Design Verification.
- Bachelor’s degree in Computer Science, Electrical Engineering, or a related field.
- Strong expertise in SystemVerilog UVM methodology.
- Experience with EDA tools for design and verification (Synopsys, Cadence).
- Proficiency in scripting languages (Python, TCL, Perl, Shell) for automation.
- Experience with formal verification, assertions, and emulation.
- Track record of first-pass success in ASIC development cycles.
- Experience verifying GPU/CPU architectures.
- Hands-on experience with PCIe, DDR, Ethernet, and other high-speed interfaces.
- Knowledge of revision control systems like Mercurial (Hg), Git, or SVN.
- Understanding of AI/ML, video, and networking ASIC verification.
- Experience developing UVM testbenches from scratch.
- Strong debugging skills with waveform analysis tools.
- Core Expertise: SystemVerilog UVM, ASIC/SoC Design Verification, Functional Testing.
- EDA Tools: Synopsys, Cadence, Formal Verification, Assertions, Emulation.
- Scripting & Automation: Python, TCL, Perl, Shell.
- High-Speed Interfaces: PCIe, DDR, Ethernet.
- Debugging & Analysis: Waveform analysis, Coverage Metrics, Root Cause Analysis.
- Soft Skills: Collaboration, Problem-Solving, Communication.
