What are the responsibilities and job description for the Senior ASIC/VLSI Synthesis and Design Engineer position at Celestial AI?
About Celestial AI
As the industry strives to meet the demands of the AI workloads, bottlenecks in data transfers between processors and memory have hindered progress. The Photonic Fabric based Memory Fabric provides an optically scalable solution to the 'Memory Wall' problem, enabling tens of Terabytes of memory capacity at full HBM bandwidths with low tens of nanoseconds of latency and extremely low power. The Photonic Fabric based Compute Fabric enables Terabyte class bandwidth between compute nodes at low latency and power. Photonic Fabric delivers a transformative leap in AI system performance, ten years more advanced than existing technologies.
Job Description :
We are seeking a highly skilled Senior ASIC / VLSI Synthesis and Design Engineer to join our team. The successful candidate will be responsible for developing and implementing complex digital designs for high-performance ASICs and SoCs. The role will involve working closely with design teams to optimize the designs for power, performance, and area while meeting stringent time-to-market constraints. The ideal candidate should have a strong background in ASIC / VLSI design flow, digital design, and synthesis methodologies, as well as experience in clock level and top-level synthesis, timing closure, gate level simulation, DFT, power analysis, memory BIST and repair. Experience with deep technology nodes and very large designs is also essential.
ESSENTIAL DUTIES AND RESPONSIBILITIES :
- Develop and implement high-performance, low-power, and area-efficient digital designs for ASICs and SoCs using industry-standard EDA tools.
- Work closely with design teams to understand the requirements and constraints of the design, and provide feedback on design feasibility, timing, and power.
- Write and implement block level and top level constraints for synthesis, perform timing closure, and gate level simulation.
- Develop and implement synthesis flows and methodologies, and drive improvements in the design process.
- Debug and resolve design issues related to synthesis, timing, power, and area.
- Design and support DFT flows, including scan insertion and ATPG.
- Optimize designs for power, performance, and area, and meet design goals within the given schedule. Implement memory BIST and repair, and support post-silicon validation.
- Implement pipelining at different levels for performance optimization and timing closure.
- Perform power analysis and optimize designs for low power.
QUALIFICATIONS :
For California location :
As an early startup experiencing explosive growth, we offer an extremely attractive total compensation package, inclusive of competitive base salary and a generous grant of our valuable early-stage equity. The target base salary for this role is approximately $175,000.00 - $195,000.00. The base salary offered may be slightly higher or lower than the target base salary, based on the final scope as determined by the depth of the experience and skills demonstrated by candidate in the interviews.
We offer great benefits (health, vision, dental and life insurance), collaborative and continuous learning work environment, where you will get a chance to work with smart and dedicated people engaged in developing the next generation architecture for high performance computing.
Celestial AI Inc. is proud to be an equal opportunity workplace and is an affirmative action employer.
LI-Onsite
Salary : $175,000 - $195,000
