What are the responsibilities and job description for the Silicon Validation Engineer position at Celestial AI?
About Celestial AI
As Generative AI continues to advance, the performance drivers for data center infrastructure are shifting from systems-on-chip (SOCs) to systems of chips. In the era of Accelerated Computing, data center bottlenecks are no longer limited to compute performance, but rather the system's interconnect bandwidth, memory bandwidth, and memory capacity. Celestial AI's Photonic Fabric™ is the next-generation interconnect technology that delivers a tenfold increase in performance and energy efficiency compared to competing solutions.
The Photonic Fabric™ is available to our customers in multiple technology offerings, including optical interface chiplets, optical interposers, and Optical Multi-chip Interconnect Bridges (OMIB). This allows customers to easily incorporate high bandwidth, low power, and low latency optical interfaces into their AI accelerators and GPUs. The technology is fully compatible with both protocol and physical layers, including standard 2.5D packaging processes. This seamless integration enables XPUs to utilize optical interconnects for both compute-to-compute and compute-to-memory fabrics, achieving bandwidths in the tens of terabits per second with nanosecond latencies.
This innovation empowers hyperscalers to enhance the efficiency and cost-effectiveness of AI processing by optimizing the XPUs required for training and inference, while significantly reducing the TCO2 impact. To bolster customer collaborations, Celestial AI is developing a Photonic Fabric ecosystem consisting of tier-1 partnerships that include custom silicon / ASIC design, system integrators, HBM memory, assembly, and packaging suppliers.
Job Description
Celestial AI is seeking a Silicon Validation Engineer to lead the bring-up and testing of mixed signal ASICs. The ideal candidate will thrive on solving complex problems in lab settings while collaborating closely with subject matter experts on SerDes, firmware, digital and analog design, and photonics. Previous experience is Serdes and high-speed data channels is a requirement.
Key Responsibilities
- Bring up, debug and characterize IP including High-Speed SerDes, USB, PLL / DLL and ADCs in test vehicles and Celestial products
- Evaluate and debug new features in PHYs, collect performance data, and resolve application / production issues
- Provide direct technical support to customers, collaborating to review designs and address inquiries
- Develop and document configurations tailored to specific system requirements
- Design and implement validation test plans
- Automate testing processes, generate test reports, and write detailed application notes
Qualifications
Location : Santa Clara, California
As an early startup experiencing explosive growth, we offer an extremely attractive total compensation package, inclusive of competitive base salary and a generous grant of our valuable early-stage equity. The target base salary for this role is approximately $175,000.00 - $200,000.00. The base salary offered may be slightly higher or lower than the target base salary, based on the final scope as determined by the depth of the experience and skills demonstrated by candidate in the interviews.
We offer great benefits (health, vision, dental and life insurance), collaborative and continuous learning work environment, where you will get a chance to work with smart and dedicated people engaged in developing the next generation architecture for high performance computing.
Celestial AI Inc. is proud to be an equal opportunity workplace and is an affirmative action employer.
LI-Onsite
Salary : $175,000 - $200,000
