What are the responsibilities and job description for the Junior IC Layout Design Engineer position at Chelsea Search Group?
Junior IC Layout Design Engineer
Onsite / hybrid
US Citizen or US Permanent Resident
Full-time/employee OT pay Benefits Bonus
Requirements:
• 3 years of experience in layout and verification tools and methodologies for RF/Analog/Mixed Signal ICs
• 3 years of experience in Cadence layout (Virtuoso, VXL) and Calibre verification (ERC, DRC, LVS)
• Demonstrated success in delivering quality work product
• FinFET or GAA preferred, but not required
• Debugging and analytical skills with complex technical concepts
• Experience in DFM hierarchical layout construction for efficient verification and integration
• Must understand techniques for managing layout dependent effects i.e. IR drop, RC delay, electron-migration, self- heating and crosstalk
• Comprehensive understanding of matching, shielding, guard rings and latch up
• Proficiency in PERL or SKILL scripting is a plus
• Strong verbal and written communication
• BSEE is a plus or AA degree in IC Layout
Responsibilities:
• Delivering on project assignments with integrity, commitment, and excellence
• Efficiently laying out sensitive RF, Analog and Mixed Signal circuits conforming to all physical design verification (PDV) requirements while balancing demanding area, performance, and power specifications
• Identifying quality and reliability improvements in IC circuit and layout design
• Supporting or performing design verification from sub-block up through top-level
• Collaborating effectively with local and remote team members
• Developing accurate layout design schedules and resource estimates
• Proactively looking for continuous improvement opportunities in the flow, layout and design methodologies
#LayoutDesign #ICLayoutDesign
Onsite / hybrid
US Citizen or US Permanent Resident
Full-time/employee OT pay Benefits Bonus
Requirements:
• 3 years of experience in layout and verification tools and methodologies for RF/Analog/Mixed Signal ICs
• 3 years of experience in Cadence layout (Virtuoso, VXL) and Calibre verification (ERC, DRC, LVS)
• Demonstrated success in delivering quality work product
• FinFET or GAA preferred, but not required
• Debugging and analytical skills with complex technical concepts
• Experience in DFM hierarchical layout construction for efficient verification and integration
• Must understand techniques for managing layout dependent effects i.e. IR drop, RC delay, electron-migration, self- heating and crosstalk
• Comprehensive understanding of matching, shielding, guard rings and latch up
• Proficiency in PERL or SKILL scripting is a plus
• Strong verbal and written communication
• BSEE is a plus or AA degree in IC Layout
Responsibilities:
• Delivering on project assignments with integrity, commitment, and excellence
• Efficiently laying out sensitive RF, Analog and Mixed Signal circuits conforming to all physical design verification (PDV) requirements while balancing demanding area, performance, and power specifications
• Identifying quality and reliability improvements in IC circuit and layout design
• Supporting or performing design verification from sub-block up through top-level
• Collaborating effectively with local and remote team members
• Developing accurate layout design schedules and resource estimates
• Proactively looking for continuous improvement opportunities in the flow, layout and design methodologies
#LayoutDesign #ICLayoutDesign
