What are the responsibilities and job description for the Senior IC Design Engineer (PLL and Clock Distribution) position at Chelsea Search Group?
Senior IC Design Engineer
San Diego, CA (onsite/hybrid)
US Citizen or US Permanent Resident (preferred)
Full-Time Health Benefits 401K Plan PTO Founder Shares
Requirements:
• High-speed time-interleaved ADCs (SAR, pipeline, TDC, etc.), RF front-end design, SerDes, miscellaneous functions (other data converters, filters, amplifiers, PLLs, power management, oscillators, etc.) in FinFET technologies.
• MS with 5 years or PhD with 3 years of experience preferred.
• Strong PLL and clock distribution experience is preferred
San Diego, CA (onsite/hybrid)
US Citizen or US Permanent Resident (preferred)
Full-Time Health Benefits 401K Plan PTO Founder Shares
Requirements:
• High-speed time-interleaved ADCs (SAR, pipeline, TDC, etc.), RF front-end design, SerDes, miscellaneous functions (other data converters, filters, amplifiers, PLLs, power management, oscillators, etc.) in FinFET technologies.
• MS with 5 years or PhD with 3 years of experience preferred.
• Strong PLL and clock distribution experience is preferred
