What are the responsibilities and job description for the Senior IC Layout Design Engineer position at Chelsea Search Group?
Senior IC Layout Design Engineer / Team Lead
Dallas, Texas (onsite / hybrid)
Full-time/Direct-hire Benefits
US Citizen or US Permanent Resident
Responsibilities:
• Leading a layout team working on mixed-signal chips and memory chips (ROIC)
• Chip level floor planning of chips including pad frame, array architecture, power bussing
• Chip level integration including IP blocks, digital blocks, and analog blocks
• Chip level verification including DRC/LVS/EMIR, parasitic extraction, and metal density fill
• Effective collaboration with local and remote team members
Requirements:
• 10 years industry experience in IC layout
• Ability to work under time constraints
• Attention to details, reading layout specifications
• Bachelor’s degree in electrical engineering or associate’s degree in Layout
• Experience in LVS and DRC
• Good understanding of the semiconductor foundry process flow
• Layout experience with memory blocks, e.g. sense amplifiers and pitch constrained row/column decoders; custom digital logic, analog blocks including bandgap, regulators, PLL, high-speed SerDes
• Solid experience in Cadence Virtuoso/Synopsys Custom Compiler Layout tool and verification tools, Calibre/PVS/IC Validator
• Strong communication and customer service skills
#LayoutDesign #ICLayout
Dallas, Texas (onsite / hybrid)
Full-time/Direct-hire Benefits
US Citizen or US Permanent Resident
Responsibilities:
• Leading a layout team working on mixed-signal chips and memory chips (ROIC)
• Chip level floor planning of chips including pad frame, array architecture, power bussing
• Chip level integration including IP blocks, digital blocks, and analog blocks
• Chip level verification including DRC/LVS/EMIR, parasitic extraction, and metal density fill
• Effective collaboration with local and remote team members
Requirements:
• 10 years industry experience in IC layout
• Ability to work under time constraints
• Attention to details, reading layout specifications
• Bachelor’s degree in electrical engineering or associate’s degree in Layout
• Experience in LVS and DRC
• Good understanding of the semiconductor foundry process flow
• Layout experience with memory blocks, e.g. sense amplifiers and pitch constrained row/column decoders; custom digital logic, analog blocks including bandgap, regulators, PLL, high-speed SerDes
• Solid experience in Cadence Virtuoso/Synopsys Custom Compiler Layout tool and verification tools, Calibre/PVS/IC Validator
• Strong communication and customer service skills
#LayoutDesign #ICLayout
