What are the responsibilities and job description for the Senior Physical Design Engineer (Cadence tools expert) position at Chelsea Search Group?
Senior Physical Design Engineer
Dallas, Texas (onsite/hybrid)
US Citizen or US Permanent Resident
Responsibilities:
• Technical lead for high-reliability, low-power VLSI design in advanced technology nodes
• Super user of industry standard Physical Design, Synthesis and Timing Analysis tools
• Architect system requirements
• Plan budget, tools and team effort and champion project needs to ensure milestones and objectives are met
• Accountable for physical design implementation of complex, low-power designs including physical-aware logic synthesis, DFT, floorplan, place and route, static timing analysis, IR Drop, EM, and physical verification
• Leverage or enhance existing digital design flow and solve design and flow issues within Cadence Genus | Innovus | Tempus
• Collaborate effectively with the full ASIC design implementation team
Qualifications:
• BSEE/MSEE with 5 years of related industry experience
• 5 years of experience with Cadence digital design tools (Genus, Innovus, Tempus)
• 5 years hands-on experience in high-reliability, low-power VLSI designs
• Production-proven experience with floor planning at chip-level with bus/pin variables, synthesis, place and route optimization, parasitic extraction, static timing analysis, low-power intent (UPF/CPF), power analysis, IR drop analysis, electromigration, physical verification and sign off
• Excellent understanding of reliability, test and power concepts & design tradeoffs required
• Skilled with Verilog/VHDL RTL and able to modify for timing or power closure
• Knowledge of MIPI, I2S, CAN protocols a plus
• Basic proficiency with programming languages such as Perl, C and TCL
#PHYSICALDESIGN
Dallas, Texas (onsite/hybrid)
US Citizen or US Permanent Resident
Responsibilities:
• Technical lead for high-reliability, low-power VLSI design in advanced technology nodes
• Super user of industry standard Physical Design, Synthesis and Timing Analysis tools
• Architect system requirements
• Plan budget, tools and team effort and champion project needs to ensure milestones and objectives are met
• Accountable for physical design implementation of complex, low-power designs including physical-aware logic synthesis, DFT, floorplan, place and route, static timing analysis, IR Drop, EM, and physical verification
• Leverage or enhance existing digital design flow and solve design and flow issues within Cadence Genus | Innovus | Tempus
• Collaborate effectively with the full ASIC design implementation team
Qualifications:
• BSEE/MSEE with 5 years of related industry experience
• 5 years of experience with Cadence digital design tools (Genus, Innovus, Tempus)
• 5 years hands-on experience in high-reliability, low-power VLSI designs
• Production-proven experience with floor planning at chip-level with bus/pin variables, synthesis, place and route optimization, parasitic extraction, static timing analysis, low-power intent (UPF/CPF), power analysis, IR drop analysis, electromigration, physical verification and sign off
• Excellent understanding of reliability, test and power concepts & design tradeoffs required
• Skilled with Verilog/VHDL RTL and able to modify for timing or power closure
• Knowledge of MIPI, I2S, CAN protocols a plus
• Basic proficiency with programming languages such as Perl, C and TCL
#PHYSICALDESIGN
Salary : $134,600 - $138,600
