ASIC Engineering Technical Leader (Design)

The application window is expected to close on 5/30/25.

This role will be based onsite out of our San Jose, CA office.

The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. We design the networking hardware for Enterprises and Service Providers of various sizes, the Public Sector, and Non-Profit Organizations across the world.

Cisco Silicon One (#CiscoSiliconOne) is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio. Come join us and take part in shaping Cisco's ground-breaking solutions by designing, developing and testing some of the most complex ASICs being developed in the industry.

Meet the Team

Our group offers a unique combination of a startup culture with the benefits of working for the leading networking company in the world. You will engage in dynamic collaboration with Senior micro-architects, designers, verification engineers and interact with cross-functional software and product teams, working together to ensure the successful deployment of the ASIC in products.

Your Impact

• Development of high-performance designs/ASICs from specification to tape-out.
• Micro-architectural definition, writing micro-architecture and implementation specifications.
• Implement Verilog RTL to meet timing and performance requirements.
• Help define, evolve, and support our design methodology.
• Collaborate with the verification, PD, DFT, Package and SW teams to develop next generation ASICs.
• Perform diagnostic and post silicon validation tests in the lab.
• Work with hardware and software teams to triage and root cause system, software, and customer failures.

Minimum Qualifications:

• Bachelor's degree in Electrical or Computer engineering and 8 years of ASIC Design experience.
• Experience with Verilog and System Verilog programming.
• Experience in architecture and micro architecture development.
• Experience delivering ASIC designs from specification to tape-out.

Preferred Qualifications:

• Master's degree in Electrical or Computer engineering and 6 years of ASIC Design experience.
• Proven experience meeting and delivering project milestones and deadlines.
• Ability to communicate technical concepts to audiences spanning executives to junior engineers.
• Demonstrated ability in troubleshooting and debugging.
• Scripting experience (Python, Perl, TCL, shell programming).

#WeAreCisco

#WeAreCisco where every individual brings their unique skills and perspectives together to pursue our purpose of powering an inclusive future for all.

Our passion is connection-we celebrate our employees' diverse set of backgrounds and focus on unlocking potential. Cisconians often experience one company, many careers where learning and development are encouraged and supported at every stage. Our technology, tools, and culture pioneered hybrid work trends, allowing all to not only give their best, but be their best.

We understand our outstanding opportunity to bring communities together and at the heart of that is our people. One-third of Cisconians collaborate in our 30 employee resource organizations, called Inclusive Communities, to connect, foster belonging, learn to be informed allies, and make a difference. Dedicated paid time off to volunteer-80 hours each year-allows us to give back to causes we are passionate about, and nearly 86% do!

Our purpose, driven by our people, is what makes us the worldwide leader in technology that powers the internet. Helping our customers reimagine their applications, secure their enterprise, transform their infrastructure, and meet their sustainability goals is what we do best. We ensure that every step we take is a step towards a more inclusive future for all. Take your next step and be you, with us!