What are the responsibilities and job description for the Senior Signal & Power Integrity Engineer position at Cisco?
The application window is expected to close on : 3 / 17 / 25
This position requires that you work at the San Jose, CA office 5 days per week as the role requires lab work.
Meet the Team
Cisco enterprise and cloud networking SI team is seeking a Senior Signal & Power Integrity Engineer for the analysis and design of high-speed components, interfaces, and power distribution networks. You will be a member of the CHG (Common Hardware Group) signal integrity team developing the Next Generations of Cisco Switch products, and participate in the definition and design of current and next generation ASIC, package, printed circuit board (PCB), and system interconnect. You will work in a larger team and work closely with system architects, logic designers, ASIC engineers, package engineers, and other versatile and knowledgeable SI / PI engineers in the creation of next-generation networking products.
Your Impact
- Working directly with ASIC and system design teams to evaluate design tradeoffs and optimize design performance / risk / cost / manufacturability
- Drive next-generation SerDes IP characterization
- Drive next-generation ASIC / system feasibility studies
- Design and analysis of multi-gigabit serial links / parallel bus in system development
- Electromagnetic modeling of complex 3-dimensional structures
- Perform pre- and post-route signal integrity analysis of both PCB and ASIC package designs
- Generating and verifying PCB layout rules
- Modeling and analyzing power delivery networks
- Performing physical measurements to collect data for design validation and simulation correlations
- Driving methodology enhancements and automation improving performance and efficiency
- Development simulation tools with EDA vendor(s) whenever needed for analysis.
- Mentor junior engineers and interns
Minimum Qualifications
Preferred Qualifications
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