What are the responsibilities and job description for the Senior Manager, ASIC Engineering - DFT position at Conductor?
To provide the best candidate experience amidst our high application volumes, each candidate is limited to 10 applications across all open jobs within a 6-month period.
Advancing the World’s Technology Together
Our technology solutions power the tools you use every day including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you’ll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries of what’s possible and powering the future.
We believe innovation and growth are driven by an inclusive culture and a diverse workforce. We’re dedicated to empowering people to be their true selves. Together, we’re building a better tomorrow for our employees, customers, partners, and communities.
What You’ll Do
This Senior Manager, ASIC Engineering position will be responsible for overall chip design execution from spec to silicon. The candidate should be familiar with Architecture, Micro Architecture, Synthesis, DFT, Design Verification, Physical Design, Timing Signoff, etc., and should be a domain expert in one or more of the above domains, especially DFT, Test, ATPG, Binning, Yield, in-system test, debug, and diagnostic needs of the design with heavy customer interactions.
Location : Onsite at our San Jose headquarters 5 days a week
Report to : Senior Director - ASIC
Job # : 42022
- Solid experience in full chip DFT architecture / spec creation for monolithic / 2.5D / 3D designs / product level testing.
- Solid experience in DFT and Test insertion, especially big die implementation.
- Solid experience in JTAG protocols, Scan, and BIST architectures like memory BIST, IO BIST, LBIST, Streaming Scan Network.
- Solid knowledge of NOC (Network on Chip from Netspeed / Arteris).
- Solid experience in post-silicon validation, validating and debugging test vectors on ATE during silicon bringup.
- Solid experience in writing DFT timing constraints.
- Solid experience of working closely with STA and PD engineers to close timing in test mode.
- Solid experience in generating, verifying, and debugging test vectors.
- Ability to work independently and mentor junior team members.
- Complete other responsibilities as assigned.
What You Bring
What We Offer
The pay range below is for all roles at this level across all US locations and functions. Individual pay rates depend on a number of factors—including the role’s function and location, as well as the individual’s knowledge, skills, experience, education, and training. We also offer incentive opportunities that reward employees based on individual and company performance.
This is in addition to our diverse package of benefits centered around the wellbeing of our employees and their loved ones. In addition to the usual Medical / Dental / Vision / 401k, our inclusive rewards plan empowers our people to care for their whole selves. An investment in your future is an investment in ours.
Base Pay Range : $180,950 - $289,050 USD
Equal Opportunity Employment Policy
Samsung Semiconductor takes pride in being an equal opportunity workplace dedicated to fostering an environment where all individuals feel valued and empowered to excel, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, genetic information, marital status, national origin, political affiliation, or veteran status.
When selecting team members, we prioritize talent and qualities such as humility, kindness, and dedication. We extend comprehensive accommodations throughout our recruiting processes for candidates with disabilities, long-term conditions, neurodivergent individuals, or those requiring pregnancy-related support. All candidates scheduled for an interview will receive guidance on requesting accommodations.
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Salary : $180,950 - $289,050
