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Senior FPGA Validation Engineer

Dawar Consulting, Inc.
San Jose, CA Full Time
POSTED ON 2/19/2025
AVAILABLE BEFORE 5/15/2025

Job Description

Our client a world leader in the semiconductor industry is looking for a Senior FPGA Validation Engineer based out of San Jose CA.

Job Duration : Long Term Contract (Possibility Of Extension)

Responsibilities :

  • Help set up FPGA / Emulation platform (Synopsys HAPS) and device modeling
  • Help set up FPGA / Emulation debugging tools Help customize the SOC design for the FPGA platform
  • Duties include modeling debugging verification and SW support
  • Work with SOC design engineers verification team systems team and software engineering to perform early prototyping debug issues and identify fixes; and
  • Support test program development chip validation and chip life until production maturity. Qualifications
  • Strong experience working with FPGAs. Familiarity with PCIe USB Ethernet SPI CPU and other commonly used blocks in SOC ASIC designs
  • Strong experience working with FPGA tools like Vivado
  • Familiar with Synopsys HAPS FPGA system preferred

Qualifications :

  • BS or MS (preferred) degree in EE / EECS / CS or equivalent.
  • 5 plus years of working experience
  • Company Benefits : Medical Dental Vision Paid Sick leave 401K

    If interested please send us your updated resume at / kavitha @dawarconsulting.com

    ServiceNOW

    Key Skills

    Python,SOC,Debugging,C / C ,FDA Regulations,Minitab,Technical Writing,GAMP,OS Kernels,Perl,cGMP,Manufacturing

    Employment Type : Full Time

    Vacancy : 1

    Monthly Salary Salary : $ 48 - 48

    Salary : $48

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