FPGA Design/Verification Release Engineer

Seeking a Release Engineer with expertise in release processes, contract deliverables, document management, and tracking within ASIC/FPGA development environments.

Job Requirements:

• Bachelor of Science or higher in Electrical Engineering, Computer Science, Computer Engineering, or equivalent experience

• 5 years of professional engineering experience

• 3 years of experience in design, debug, and/or verification of ASICs or FPGAs

• Ability to obtain and maintain a DoD Secret clearance (U.S. Citizenship required)

• Knowledge of Contract Deliverable Requirements List (CDRL), Subcontract Deliverable Requirements List (SDRL), and Statement of Work (SOW)

• Understanding of industry-standard versioning schemes (e.g., Semantic Versioning)

• Experience with source control (e.g., Git, Subversion) and build management (e.g., GitLab Releases, Nexus, Artifactory)

• Proficiency in Linux environments

Preferred Skills:

• Experience with Microsoft Office and Microsoft Project

• Familiarity with Atlassian Jira for tracking and managing workflows

• Ability to obtain a TS/SCI clearance

• Knowledge of Python and SQL for data analysis and automation

Job Responsibilities:

• Collaborate with Technical Leaders to develop and review CDRL items

• Evaluate Statement of Work (SOW) and ensure all required CDRLs are relevant to FPGA development

• Establish release schedules, track CDRL deliverables, and ensure on-time submission

• Work with Data Management teams to synchronize schedules and adjudicate CDRL approvals

• Coordinate with FPGA Technical Leads to ensure awareness and tracking of upcoming releases

• Ensure CDRL documents meet Data Item Description (DID) requirements for content and format

• Align CDRL schedules with the Integrated Master Schedule (IMS)

• Report CDRL metrics and upcoming deliverables in weekly leadership meetings

• Manage FPGA document approvals and track progress in document management systems

• Oversee FPGA release processes, ensuring circuitware delivery aligns with customer expectations

• Provide release metrics and projections for Technical Leads and Management

• Assist in proposal creation, leveraging historical project data

• Set up and maintain development and release tracking infrastructure for consistency

• Communicate effectively with ASIC/FPGA engineers, Technical Leads, and Managers, ensuring alignment with semiconductor development lifecycles.

Pay: $85-100
Benefit offerings include medical, dental, vision, term life insurance, short-term disability insurance, additional voluntary benefits, commuter benefits and 401K plan. Our program provides employees the flexibility to choose the type of coverage that meets their individual needs. Available paid leave may include Paid Sick Leave, where required by law; any other paid leave required by Federal, State or local law; and Holiday pay upon meeting eligibility criteria. Disclaimer: These benefit offerings do not apply to client-recruited jobs and jobs which are direct hire to a client.

Pay Details: $85.00 to $100.00 per hour

Benefit offerings available for our associates include medical, dental, vision, life insurance, short-term disability, additional voluntary benefits, EAP program, commuter benefits and a 401K plan. Our benefit offerings provide employees the flexibility to choose the type of coverage that meets their individual needs. In addition, our associates may be eligible for paid leave including Paid Sick Leave or any other paid leave required by Federal, State, or local law, as well as Holiday pay where applicable.

Equal Opportunity Employer/Veterans/Disabled

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The Company will consider qualified applicants with arrest and conviction records in accordance with federal, state, and local laws and/or security clearance requirements, including, as applicable:

• The California Fair Chance Act
• Los Angeles City Fair Chance Ordinance
• Los Angeles County Fair Chance Ordinance for Employers
• San Francisco Fair Chance Ordinance