What are the responsibilities and job description for the Top Level Microarchitecture position at Eridu AI?
About Eridu AI
Eridu AI is a Silicon Valley hardware startup focused on accelerating training and inference performance for large AI models. Today’s AI model performance is often gated by infrastructure bottlenecks. Eridu AI introduces multiple industry-first innovations across semiconductors, software and systems to deliver solutions that improves AI data center performance to increase GPU utilization while simultaneously reducing capex and power. Eridu AI’s solution and value proposition have been widely validated with several hyperscalers.
The company is led by a veteran team of Silicon Valley executives and engineers with decades of experience in state-of-the-art semiconductors, optics, software, and systems, including serial entrepreneur Drew Perkins, co-founder of Infinera (NASDAQ: INFN), Lightera (acq. by Ciena), Gainspeed (acq. by Nokia) and Mojo Vision (World’s leading micro-LED display company and developer of the first augmented reality contact lens).
Position Overview
We are seeking a Top Level Microarchitecture Engineer to define and implement our industry-leading Networking IC. If you're a highly motivated self-starter eager to solve real-world problems, this is a unique opportunity to shape the future of AI Networking. As part of the Design Group, you will be responsible for defining, specifying, architecting, executing, and productizing cutting-edge Networking devices.
Responsibilities
At Eridu AI, you’ll have the opportunity to shape the future of AI infrastructure, working with a world-class team on groundbreaking technology that pushes the boundaries of AI performance. Your contributions will directly impact the next generation of AI networking solutions, transforming data center capabilities.
The starting base salary for the selected candidate will be established based on their relevant skills, experience, qualifications, work location, market trends, and the compensation of employees in comparable roles.
The Pay Range For This Role Is
230,000 - 325,000 USD per year(San Francisco Bay Area)
Eridu AI is a Silicon Valley hardware startup focused on accelerating training and inference performance for large AI models. Today’s AI model performance is often gated by infrastructure bottlenecks. Eridu AI introduces multiple industry-first innovations across semiconductors, software and systems to deliver solutions that improves AI data center performance to increase GPU utilization while simultaneously reducing capex and power. Eridu AI’s solution and value proposition have been widely validated with several hyperscalers.
The company is led by a veteran team of Silicon Valley executives and engineers with decades of experience in state-of-the-art semiconductors, optics, software, and systems, including serial entrepreneur Drew Perkins, co-founder of Infinera (NASDAQ: INFN), Lightera (acq. by Ciena), Gainspeed (acq. by Nokia) and Mojo Vision (World’s leading micro-LED display company and developer of the first augmented reality contact lens).
Position Overview
We are seeking a Top Level Microarchitecture Engineer to define and implement our industry-leading Networking IC. If you're a highly motivated self-starter eager to solve real-world problems, this is a unique opportunity to shape the future of AI Networking. As part of the Design Group, you will be responsible for defining, specifying, architecting, executing, and productizing cutting-edge Networking devices.
Responsibilities
- Design and architect microarchitecture for Ethernet packet processing engine.
- Collaborate with cross-functional teams, including hardware design, software engineering, and product management, to define requirements and deliver high-performance solutions.
- Conduct feasibility studies and performance analysis to optimize packet processing throughput, latency, and power efficiency.
- Implement and verify microarchitecture designs using simulation tools and FPGA emulation.
- Work with Chip Architects and Physical Design teams to develop the appropriate microarchitecture.
- Develop a coherent test plan in collaboration with the design verification group.
- Investigate and resolve complex issues working closely with cross-functional teams including hardware engineers, firmware developers, and system architects.
- MSEE with at least 15 years of experience.
- Expertise in clocks and resets, including the development of clock architecture and reset logic for various chips, and a comprehensive understanding of source synchronous logic.
- Proficient in ECC/CRC and other bit error remedial techniques. Fluent in control and data path structured design on very large chips. Strong understanding of timing and latency tradeoffs, device variation, and clock skew concepts.
- Expertise in synchronization techniques such as FIFOs and synchronizers.
- Solid understanding of FPGA or ASIC design methodologies, including synthesis, simulation, and verification tools (e.g., Verilog, VHDL, Synopsys, Cadence).
- Knowledge of Ethernet and IP networking protocols, with experience in TCP/UDP, VLANs, MPLS, and other relevant protocols as a plus.
- Experience in developing a packet processor subsystem on a networking chip.
- Strong analytical and problem-solving abilities, with meticulous attention to detail in troubleshooting and debugging complex networking issues.
- Excellent verbal and written communication skills, with the ability to collaborate effectively in a team environment and present technical information to diverse audiences.
At Eridu AI, you’ll have the opportunity to shape the future of AI infrastructure, working with a world-class team on groundbreaking technology that pushes the boundaries of AI performance. Your contributions will directly impact the next generation of AI networking solutions, transforming data center capabilities.
The starting base salary for the selected candidate will be established based on their relevant skills, experience, qualifications, work location, market trends, and the compensation of employees in comparable roles.
The Pay Range For This Role Is
230,000 - 325,000 USD per year(San Francisco Bay Area)
