What are the responsibilities and job description for the Senior Hardware Engineer, Physical Design - MTV position at Google DeepMind?
At Google DeepMind, we value diversity of experience, knowledge, backgrounds and perspectives and harness these qualities to create extraordinary impact. We are committed to equal employment opportunity regardless of sex, race, religion or belief, ethnic or national origin, disability, age, citizenship, marital, domestic or civil partnership status, sexual orientation, gender identity, pregnancy, or related condition (including breastfeeding) or any other basis as protected by applicable law. If you have a disability or additional need that requires accommodation, please do not hesitate to let us know.
Snapshot :
At Google DeepMind, we've built a unique culture and work environment where long-term ambitious research can flourish. We are seeking a highly motivated Hardware Engineer to join our team and contribute to the development of groundbreaking silicon for machine learning acceleration.
About us :
Artificial Intelligence could be one of humanity’s most useful inventions. At Google DeepMind, we’re a team of scientists, engineers, machine learning experts, and more, working together to advance the state of the art in artificial intelligence. We use our technologies for widespread public benefit and scientific discovery, and collaborate with others on critical challenges, ensuring safety and ethics are the highest priority.
About you :
We seek out individuals who thrive in ambiguity and who are willing to help out with whatever moves silicon design and architecture forward. We regularly need to invent novel solutions to problems and often change course if our ideas don’t work out, so flexibility and adaptability to work on any project is a must.
The Role :
We are seeking a talented and highly motivated hardware engineer to join our GenAI technical infrastructure research hardware team. You will have the opportunity to partake in cutting-edge architecture exploration that will shape the future of machine learning acceleration.
Responsibilities :
- Work in a fast and interdisciplinary team bringing together experts from Machine Learning, Hardware, Programming Languages, and Systems.
- Collaborate closely with HW architects and design engineers, rapidly iterating experimental designs and providing reliable feedback on performance, power, and area of different design options.
- Drive architectural feasibility studies and explore RTL / design tradeoffs for physical design closure.
- Perform block-level physical implementation steps including synthesis, floorplanning, place and route, power / clock distribution, congestion analysis, STA, timing closure, EM-IR, PV, CDC analysis, LEC, etc.
- Provide actionable feedback to silicon design engineers and architects for design improvements.
- Participate in establishing physical design methodologies, flow automation, chip floorplan, power / clock distribution, chip assembly, and P&R, timing closure.
- Develop physical design methodologies and automation scripts for various implementation steps.
- Perform technical evaluations of vendors, process nodes, IP, and chip design tools.
Minimum Qualifications :
Preferred Qualifications :
The US base salary range for this full-time position is between $142,000 - 219,000
Application deadline : 12pm PST Friday February 7th, 2025.
Note : In the event your application is successful and an offer of employment is made to you, any offer of employment will be conditional on the results of a background check, performed by a third party acting on our behalf. For more information on how we handle your data, please see our Applicant and Candidate Privacy Policy
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Salary : $142,000 - $219,000
