Principal FPGA System Design Engineer

InnoPhase Inc., DBA GreenWave Radios™, is at the forefront of innovation in Open RAN digital radios. Our cutting-edge solutions, powered by the Hermes64 RF SoC, are designed to enhance network energy efficiency while dramatically reducing operational expenses, with purpose-built silicon that is the heart of ORAN-based active antenna arrays.

Headquartered in San Diego, California, GreenWave Radios™ has established itself as a pioneer in delivering power-efficient digital-to-RF solutions. The company is supported by a talented team of over 100 engineers spread across four global R&D facilities. With an extensive portfolio of more than 120 global patents, GreenWave Radios™ continues to push the boundaries of radio technology and innovation.

To learn more about GreenWave Radios™ and hear what our employees have to say, visit the GreenWave™ certification profile at GreatPlacetoWork.com or explore our Home - GreenWave Radios website.

Principal Engineer, FPGA System Design: You will be responsible for providing technical contributions in developing novel/game-changing cellular infrastructure radio Front Haul Gateway (FHGW) FPGA and contributing to our ASIC solutions. You will be responsible for our solutions' features, architectures, device functional specifications, and performance. You will work closely with a multi-site team of FPGA design, verification, and software engineers to deliver production-quality programmable logic designs with embedded Linux-based wireless communications software to enable our market-leading cellular infrastructure radio solutions.

This full-time position is based in Irvine, CA.

Key Responsibilities

• Work with a team of SW engineers to define, develop, and verify embedded Linux-based SW for Cellular base station radios on custom FPGA designs, including Applications and Drivers for an embedded Linux-based environment and follow-on ASIC solutions.
• Establish unit-level design, implementation, and test strategies
• Perform Synthesis, P&R, and generated FPGA images
• Bring up emulation platform with SW and system teams
• Support integration, test, and debug software for timely closure
• Develop and own functional blocks to be used on multiple platforms
• Hands-on debug capability using lab equipment and JTAG
• Contribute to/review specifications and architectures
• FPGA front-to-back digital design and verification – RTL through physical implementation
  
  

Job Requirements

• MS in EE/CS or equivalent required
• 20 years’ of working with FPGA architecture, implementation, and verification
• Develop FPGA design specifications, communicate and verify these specifications with the RF/FW designers
• Debug designs and provide timely closure
• Perform Synthesis, P&R and generated FPGA images
• Experience with embedded systems, wireless protocols, power management, signal processing and standard digital interfaces
• RTL design knowledge (Verilog/VHDL) and SystemVerilog
• Knowledge of front-end tools (Verilog simulators, linters, clock-domain crossing checkers)
• Proven knowledge of synthesis, static timing, F2B digital SoC design flow
• Experience with development for PetaLinux (Xilinx-based Linux SW package) incl. development workflow incorporating Xilinx Vivado & Xilinx SDK
• Experience with Xilinx Zynq platform, Vivado Tools (10G Ethernet IP)Experience with Embedded Linux Kernel, Driver, and Application development
• Experience building and integrating SW for a multi-vendor environment e.g. some internal custom SW Xilinx IP 3rd-party / open source SW
• Experience with ARM or similar embedded SoC development environments
• Excellent debug skills
• Comfortable with configuration management and version control
• Able to work productively and independently
• Experience with C, C , or Python
  
  

Desirable Skills

• Prior experience with cellular infrastructure radio development
• Familiarity with ORAN M/C/S/U plane
• Familiarity with netconf2, netopeer2 client/server, yang, SysRepo, SyncE, PTP
• Experienced in RTOS principles and concepts, and hands-on experience in any RTOS
• Prior System on a Chip (SoC) ASIC product development experience
• Good understanding of cellular wireless protocols (MAC/PHY)
• Experience using command-line Git, GitLab and Jira tools
• Able to work effectively with incomplete or changing requirements
• Strong knowledge of mixed-signal concepts
  
  

Compensation And Benefits

At InnoPhase, dba GreenWave Radios, our compensation package includes base pay and pre-IPO stock options. The base pay range for this role is between $140K-$225K. Your base pay will depend on the market, interview results, skills, qualifications, experience, education, and location. Our employee benefits include a comprehensive group health plan, matching 401(k), training reimbursement, and various paid leaves (vacation, sick, holidays, maternity/paternity leave, jury). Visit our website to learn more about our employee benefits.