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Hardware Design Engineer 2

HireTalent
Mountain View, CA Full Time
POSTED ON 4/3/2025
AVAILABLE BEFORE 5/2/2025

Job Title : Hardware Design Engineer 2

Location : Silicon Valley, CA

Duration : 4 Months on W2

Summary :

The main function of a hardware engineer is to research, design, develop, test computer or computer-related equipment for commercial, industrial, military, or scientific use. A typical hardware engineer is responsible for the manufacture and installation of computer or computer-related equipment and components.

Job Responsibilities :

Analyze information to determine plan layout, including type of computers and peripheral equipment modifications.

Assemble and modify existing pieces of equipment to meet special needs.

Build, test, and modify product prototypes using working models or theoretical models constructed with computer simulation.

Evaluate factors such as reporting formats required, cost constraints, and need for security restrictions to determine hardware configuration.

Monitor functioning of equipment and make necessary modifications to ensure system operates in conformance with specifications.

Skills :

Creativity, verbal and written communication skills, analytical and problem solving ability.

Team player and detail oriented.

Basic knowledge of design techniques, tools and principles involved in production of precision technical plans, blueprints, drawings and models.

Basic knowledge of the practical application of engineering science and technology.

Basic knowledge of circuit boards, processors, chips, electronic equipment, and computer hardware and software, including applications and programming.

Previous experience with computer applications and design software related to engineering field.

Education / Experience :

2-4 years experience required.

Top 3 Hard Skills Required Years of Experience

1. Minimum 2 years experience with Knowledge of computer architecture.

2. Minimum 2 years experience with Ability to program in C / C and Python.

3. Minimum 2 years experience with Exposure to simulation in a pre-silicon environment

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