Demo

Staff ASIC Design Engineer

hireVouch
Remote, OR Remote Full Time
POSTED ON 4/15/2025
AVAILABLE BEFORE 5/7/2025

We are looking for a  Staff ASIC Design Engineer  to contribute to a team developing IP for both ASICs and FPGAs. The ideal candidate is a strong communicator, creative, a critical thinker, and able to analyze and resolve complex issues.

Responsibilities

Apply industry best practices in ASIC development to achieve best in class designs

  • Design, propose, and oversee the analysis / evaluation of hardware architectures
  • Design and code RTL modules written in Verilog / SystemVerilog
  • Simulate and perform hardware-based testing, debug, and verification
  • Scripting and basic software development in support of hardware design
  • Apply Agile development methodologies including code reviews, sprint planning, and frequent deployment

Requirements

B.S, M.S, or Ph.D in Electrical Engineering, Computer Engineering or Computer Science

  • Track record of successful tape outs in advanced process nodes
  • 10 years of experience in ASIC design
  • Experience in ASIC design methodologies, including code quality checking, synthesis, physical design, and power estimation design tools
  • Strong knowledge with RTL programming languages Verilog / SystemVerilog (preferred), or VHDL
  • Ability to read and write code in TCL / Python (C, C are assets)
  • Preferred Skills & Experience

    Deep experience with ASIC or FPGA timing closure and physical design

  • Working experience with AMBA protocols, PCIe, UCIe, and HBM will be an asset
  • Experience with Agile development methodologies
  • Experience in technical leadership of small teams
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