What are the responsibilities and job description for the Design Verification Engineer with Synopsys / Cadence EDA Design position at IBA Infotech Inc.?
Job Description
Job Description
Company Description
We at IBA InfoTech find the Hidden Talent across the globe. We connect caliber candidates with leading companies in contract, contract-to-hire and direct-hire positions in various industries - Oil & Gas, Energy, Telecommunications, Transportation, Business & Finance, Retail, Hospitality and Insurance.
Job Description
Role : ASIC Design Verification Engineer
Location : Redmond, WA - Onsite Role
Job Type : Contract
Interview Mode : Video
We are hiring a SOC Design Verification Engineer for a contract position!
Responsibilities :
Define and implement SoC verification plans and build verification test benches.
Develop functional tests based on verification test plans.
Drive Design Verification to closure based on defined verification metrics.
Debug, root-cause, and resolve functional failures in design.
Collaborate with cross-functional teams to ensure the highest design quality.
Develop and drive continuous Design Verification improvements using the latest methodologies, tools, and technologies.
Minimum Qualifications :
Track record of 'first-pass success' in ASIC development cycles.
Bachelor's degree in Computer Science, Computer Engineering, or a relevant technical field, or equivalent practical experience.
8 to 10 years of hands-on experience in SystemVerilog / UVM methodology.
Experience with SV Assertions, Formal, Emulation.
Experience with EDA tools and scripting (Python, TCL, Perl, Shell) for verification environments.
Preferred Qualifications :
Experience verifying GPU / CPU designs.
Development of UVM-based verification environments from scratch.
Design verification of Data-center applications like Video, AI / ML, and Networking designs.
Experience with revision control systems like Mercurial(Hg), Git, or SVN.
IP or integration verification of high-speed interfaces like PCIe, DDR, Ethernet.
Experience working across and building relationships with cross-functional teams.
SOCDesignVerification #SystemVerilog #UVM #EDA #ASICDevelopment #Python #TCL #Perl #Synopsys #Cadence #RemoteWork #Contract
Additional Information
All your information will be kept confidential according to EEO guidelines.
