RFIC Layout Lead

This an opportunity for an experienced RFIC Layout lead to join a dynamic team at the forefront of developing cutting-edge communication technologies, including Ultra Low Power MIMO Transceivers. This is your chance to contribute to the next generation of wireless solutions for Wi-Fi, Bluetooth, and UWB.

As a RFIC Layout Lead you will lead and coordinate the design and verification of high-end Analog, RF, and Mixed-Signal Integrated Circuits. This role combines technical expertise with leadership responsibilities, offering a unique opportunity to shape the future of wireless communication technology.

The Main Responsibilities Of The RFIC Layout Lead Include

• Lead cross-team planning, collaboration, and alignment to ensure smooth workflow.
• Oversee the layout and verification processes, including DRC, LVS, EMIR, and Self-Heating analysis.
• Take ownership of chip-level layout, ensuring high-quality implementations.
• Debug and resolve DRC/LVS/EMIR verification issues.
• Develop layout documentation reports and contribute to design reviews.
• Mentor and guide layout engineers, ensuring excellence in top-level integration.
  
  

The Requirements Of The RFIC Layout Lead Include

• Extensive experience in custom layout design, especially in CMOS nodes (22nm and below).
• Deep understanding of analog layout techniques, including matching, parasitic minimisation, and low-power design.
• Familiarity with electromigration, coupling, and crosstalk challenges.
• Proficiency in layout tools such as Cadence, Siemens DRC/LVS/Extraction, and Synopsys Custom Compiler.
• Strong grasp of advanced process effects (LOD, WPE) and experience with guard rings, DNW, and trench isolation.
• Leadership Abilities : Proven capability to lead other layout engineers and mange top-level intergration.
  
  

If this role is of interest, please contact Parm for more information!