Demo

ASIC Engineer

ideaVat
San Jose, CA Full Time
POSTED ON 1/13/2025
AVAILABLE BEFORE 3/28/2025

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With over 20 man years of contingent staffing experience, the management & execution team is committed to provide customized staffing solutions to employers / hiring managers, helping them identify key talents. Emergent technology staffing (UI / UX developers & designers, Mobility & Cloud Engineers, Big Data / Hadoop developers & architects…& more) remains our primary focus!

Job Description

Job Title : ASIC Engineer

Location : San Jose, CA

Duration : 6 Months

Minimum Required Skills :

ASIC Design, FPGA, RTL Design, Chip Architecture, ASIC, Implementation, Synthesis / Conformal (Cadence Tool for formal verification)

Description :

  • Should have 2-5 years of experience in FPGA / ASIC Development
  • Build RTL designs of digital circuits using VHDL and System Verilog
  • Perform frontend design development and integration of large ASIC designs
  • Collaborate with Chip Architecture, Design Verification, and Physical Design teams to achieve first tapeout success.
  • Write design documents including high level interface descriptions and design descriptions.
  • Write function test cases and test benches to verify functionality of designs
  • Team work and proactive sharing of knowledge
  • Comfortable working in a fast paced environment.

Qualifications

ASIC Design, FPGA, RTL Design, Chip Architecture, ASIC, Implementation, Synthesis / Conformal (Cadence Tool for formal verification)

Additional Information

All your information will be kept confidential according to EEO guidelines.

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