What are the responsibilities and job description for the ASIC Design Verification Engineer position at iFlow Inc.?
Job Title: ASIC Design Verification Engineer
Location: Remote (Pacific Zone Candidate Preferred)
Duration: 5 Months with Possible Extension upto 18 months
Candidate should have 7 years of hands-on experience in ASIC Design Verification with strong UVM Testbench coding experience.
ROLE OVERVIEW:
You will join a cutting-edge team working on the next generation of AI chip technology, publicly known as MAIA. This position focuses heavily on Universal Verification Methodology (UVM) for block-level verification. The role involves collaboration, problem-solving, and working on innovative AI chip design challenges.
RESPONSIBILITIES
• Define verification strategies, requirements, and test environments for IP-level verification.
• Develop comprehensive test plans and write test cases for complete feature coverage.
• Own the verification of complex IPs, including:
o Creating UVM components and environments from scratch.
o Debugging failures and addressing root cause issues.
o Running and maintaining regression suites and closing coverage.
• Write and implement UVM components, including scoreboards, sequences, constraints, assertions, and functional coverage.
• Build and maintain verification infrastructure, including makefiles and scripts.
• Collaborate using Agile methodologies (e.g., sprint planning, code reviews).
• Lead and mentor a small team of verification engineers.
• Work across teams and geographies to achieve project goals.
QUALIFICATIONS
Experience:
• 7-10 years of experience in hardware design verification with a focus on UVM.
Required Skills:
1. ASIC Design Verification: Minimum 7 years, with demonstrated expertise in ensuring accuracy and adherence to project timelines.
2. Unit-Level Verification: Minimum 7 years, including hands-on experience in block-level verification.
3. UVM Expertise: Proven proficiency in the UVM library and methodology, as it is the industry standard.
Additional Skills:
• Strong foundation in Object-Oriented Programming (OOP) concepts.
• Analytical and problem-solving abilities with attention to detail.
• Effective verbal and written communication skills.
• Ability to adapt and work collaboratively in dynamic environments.
EDUCATION:
• Bachelor’s degree in engineering preferred but not required for candidates with relevant experience.
DISQUALIFIERS:
• Lack of OOP knowledge.
• No prior experience with UVM.
KEY HIGHLIGHTS OF THE ROLE
• Be part of a transformative project in AI chip development.
• Work in a collaborative team that values innovative problem-solving.
• Opportunities for professional growth and learning in a cutting-edge field.
PERFORMANCE EXPECTATIONS
• Deliver high-quality verification work, with a focus on adaptability and efficiency.
• Contribute to the team’s dynamic approach to solving design challenges.
