What are the responsibilities and job description for the Principal, ATE Test Engineer position at indie Semiconductor?
Job Description
As a Test Engineer, you will be responsible for developing and implementing test programs for the Advantest 93K SmartScale/ExaScale platform. Your role will include the following key responsibilities:
- Test program development from requirements, schedule, ATE HW (CP & FT), Qaul test program, characterization test program, and optimized production test program.
- Test Engineering Lead for SOC, MS, and PMIC tests. RF test experience a plus.
- Collaborate closely with Test Architects, Product Development, and Product Engineering to integrate Design-for-Test (DfX) into new products.
- Analyze and summarize debug findings, proposing improvements for DfX features and test coverage.
- Based on the overall test strategy, develop test concepts, programs, and hardware for both wafer and final test in accordance with Automotive requirements specifications.
- Take ownership of achieving test engineering milestones: Test coverage, Test Development schedule, and cost of test.
- Participate in the creation and simulation of digital and analog test patterns and generate tester-specific test vectors.
- Define and develop new test methods and techniques.
- Contribute to the development of production and characterization hardware for automatic test equipment with high test coverage (wafer and final test).
- Analyze test data and report results to the IC design teams.
- Oversee the introduction and release of mass-production-related software and hardware.
- Understand new chip features and define applicable coverage for the test environment.
- Serve as the first point of contact for failure analysis, identifying issues related to setup, code, artifacts, silicon, logic/physical blocks, and more.
Key Qualifications
- Bachelor’s degree (or equivalent) in Electrical Engineering or Computer Science with EE minor.
- 10 years of ATE test engineering experience, with preferred knowledge of the V93000 SOC Tester SMT8.
- Strong analytical, planning, and organizational skills.
- Skilled in creating compliance matrices, plotting results, and presenting data.
- Exposure to post-silicon validation, silicon bring-up, testing/debugging, root cause analysis of circuit marginalities, product engineering, and foundry manufacturing.
- Experience working with cross-functional teams.
- System-level and RF/SOC experience is a plus.
- Strong programming skills for writing and debugging test programs and resolving ATE hardware-related issues.
- Proficiency in scripting languages (e.g., Perl, Python) and high-level languages (e.g., C/C , Java).
- Comfortable working primarily in a lab environment with strong experimental techniques for problem localization and root cause analysis.
- Excellent data analysis skills and attention to detail.
- Knowledge in load board design, testing, and debugging.
Preferred Experience (in one or more areas)
- Chip design background in circuit/physical design (e.g., timing closure, power) or design verification (DV), correlating software signatures to block-level tests.
- Post-silicon physical debug experience in speed-path/Vmin, memory arrays, clocking, or yield improvements.
- Post-silicon logic debug experience, including exercising various DfX features, analyzing scan/memory dumps, and suggesting tests at both the system and DV levels.
- Product engineering experience, with familiarity in ATE coverage, margin, binning, and scan pattern generation.
- Knowledge of MIPI protocols.
- RF test experience.
